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Cortex-A17: Implement workaround for errata 852423 

Change-Id: I3a101e540f0b134ecf9a51fa3d7d8e3d0369b297
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
This commit is contained in:
Ambroise Vincent 2019-03-04 13:20:56 +00:00
parent 0b64c19485
commit be10dcde52
3 changed files with 47 additions and 0 deletions
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3
docs/cpu-specific-build-macros.rst
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@ -84,6 +84,9 @@ For Cortex-A17, the following errata build flags are defined :
- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17
CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17
CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
For Cortex-A53, the following errata build flags are defined :
- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all

36
lib/cpus/aarch32/cortex_a17.S
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@ -63,6 +63,34 @@ func check_errata_852421
b cpu_rev_var_ls
endfunc check_errata_852421
/* ----------------------------------------------------
* Errata Workaround for Cortex A17 Errata #852423.
* This applies only to revision <= r1p2 of Cortex A17.
* Inputs:
* r0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: r0-r3
* ----------------------------------------------------
*/
func errata_a17_852423_wa
/*
* Compare r0 against revision r1p2
*/
mov r2, lr
bl check_errata_852423
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
ldcopr r0, CORTEX_A17_IMP_DEF_REG1
orr r0, r0, #(1<<12)
stcopr r0, CORTEX_A17_IMP_DEF_REG1
1:
bx r2
endfunc errata_a17_852423_wa
func check_errata_852423
mov r1, #0x12
b cpu_rev_var_ls
endfunc check_errata_852423
func check_errata_cve_2017_5715
#if WORKAROUND_CVE_2017_5715
mov r0, #ERRATA_APPLIES
@ -87,6 +115,7 @@ func cortex_a17_errata_report
* checking functions of each errata.
*/
report_errata ERRATA_A17_852421, cortex_a17, 852421
report_errata ERRATA_A17_852423, cortex_a17, 852423
report_errata WORKAROUND_CVE_2017_5715, cortex_a17, cve_2017_5715
pop {r12, lr}
@ -97,11 +126,18 @@ endfunc cortex_a17_errata_report
func cortex_a17_reset_func
mov r5, lr
bl cpu_get_rev_var
mov r4, r0
#if ERRATA_A17_852421
mov r0, r4
bl errata_a17_852421_wa
#endif
#if ERRATA_A17_852423
mov r0, r4
bl errata_a17_852423_wa
#endif
#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715
ldr r0, =workaround_bpiall_runtime_exceptions
stcopr r0, VBAR

8
lib/cpus/cpu-ops.mk
View File

@ -65,6 +65,10 @@ ERRATA_A15_827671 ?=0
# only to revision <= r1p2 of the Cortex A17 cpu.
ERRATA_A17_852421 ?=0
# Flag to apply erratum 852423 workaround during reset. This erratum applies
# only to revision <= r1p2 of the Cortex A17 cpu.
ERRATA_A17_852423 ?=0
# Flag to apply erratum 819472 workaround during reset. This erratum applies
# only to revision <= r0p1 of the Cortex A53 cpu.
ERRATA_A53_819472 ?=0
@ -220,6 +224,10 @@ $(eval $(call add_define,ERRATA_A15_827671))
$(eval $(call assert_boolean,ERRATA_A17_852421))
$(eval $(call add_define,ERRATA_A17_852421))
# Process ERRATA_A17_852423 flag
$(eval $(call assert_boolean,ERRATA_A17_852423))
$(eval $(call add_define,ERRATA_A17_852423))
# Process ERRATA_A53_819472 flag
$(eval $(call assert_boolean,ERRATA_A53_819472))
$(eval $(call add_define,ERRATA_A53_819472))