Merge "feat(stm32mp1): preserve the PLL4 settings for USB boot" into integration
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be1d8b24f5
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@ -1744,6 +1744,8 @@ int stm32mp1_clk_init(void)
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bool pll4_bootrom = false;
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const fdt32_t *pkcs_cell;
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void *fdt;
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int stgen_p = stm32mp1_clk_get_parent(STGEN_K);
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int usbphy_p = stm32mp1_clk_get_parent(USBPHY_K);
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if (fdt_get_address(&fdt) == 0) {
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return -FDT_ERR_NOTFOUND;
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@ -1843,6 +1845,13 @@ int stm32mp1_clk_init(void)
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pllcfg[_PLL4],
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plloff[_PLL4]);
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}
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/* Don't initialize PLL4, when used by BOOTROM */
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if ((stm32mp_get_boot_itf_selected() ==
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BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) &&
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((stgen_p == (int)_PLL4_R) || (usbphy_p == (int)_PLL4_R))) {
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pll4_bootrom = true;
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pll4_preserve = true;
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}
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for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
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if (((i == _PLL3) && pll3_preserve) ||
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@ -1994,6 +2003,11 @@ int stm32mp1_clk_init(void)
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if (pkcs_cell != NULL) {
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bool ckper_disabled = false;
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uint32_t j;
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uint32_t usbreg_bootrom = 0U;
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if (pll4_bootrom) {
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usbreg_bootrom = mmio_read_32(rcc_base + RCC_USBCKSELR);
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}
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for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) {
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uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]);
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@ -2014,6 +2028,25 @@ int stm32mp1_clk_init(void)
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if (ckper_disabled) {
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stm32mp1_pkcs_config(CLK_CKPER_DISABLED);
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}
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if (pll4_bootrom) {
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uint32_t usbreg_value, usbreg_mask;
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const struct stm32mp1_clk_sel *sel;
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sel = clk_sel_ref(_USBPHY_SEL);
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usbreg_mask = (uint32_t)sel->msk << sel->src;
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sel = clk_sel_ref(_USBO_SEL);
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usbreg_mask |= (uint32_t)sel->msk << sel->src;
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usbreg_value = mmio_read_32(rcc_base + RCC_USBCKSELR) &
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usbreg_mask;
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usbreg_bootrom &= usbreg_mask;
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if (usbreg_bootrom != usbreg_value) {
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VERBOSE("forbidden new USB clk path\n");
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VERBOSE("vs bootrom on USB boot\n");
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return -FDT_ERR_BADVALUE;
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}
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}
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}
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/* Switch OFF HSI if not found in device-tree */
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