refactor(drivers/marvell/comphy-3700): simplify usage of indirect access on lane2
For code cleanup add two helper functions comphy_sata_set_indirect() and comphy_usb_set_indirect() for SATA and USB 3.0 modes and remove additional 'mode' argument which is not needed anymore. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I23146f569db318dbaed5d411d7d175abf6efff85
This commit is contained in:
Pali Rohár
parent
fc299ce07b
commit
be33dce740
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@ -214,7 +214,7 @@ static int mvebu_a3700_comphy_get_mode(uint8_t comphy_index)
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/* It is only used for SATA and USB3 on comphy lane2. */
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static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data,
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uint16_t mask, int mode)
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uint16_t mask, bool is_sata)
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{
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/*
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* When Lane 2 PHY is for USB3, access the PHY registers
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@ -224,21 +224,33 @@ static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data,
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* within the SATA Host Controller registers, Lane 2 base register
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* offset is 0x200
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*/
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if (mode == COMPHY_UNUSED)
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return;
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if (mode == COMPHY_SATA_MODE)
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if (is_sata) {
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mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, offset);
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else
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} else {
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mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET,
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offset + USB3PHY_LANE2_REG_BASE_OFFSET);
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}
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reg_set(addr + COMPHY_LANE2_INDIR_DATA_OFFSET, data, mask);
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}
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/* It is only used USB3 direct access not on comphy lane2. */
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/* It is only used for SATA on comphy lane2. */
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static void comphy_sata_set_indirect(uintptr_t addr, uint32_t reg_offset,
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uint16_t data, uint16_t mask)
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{
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comphy_set_indirect(addr, reg_offset, data, mask, true);
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}
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/* It is only used for USB3 indirect access on comphy lane2. */
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static void comphy_usb3_set_indirect(uintptr_t addr, uint32_t reg_offset,
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uint16_t data, uint16_t mask)
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{
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comphy_set_indirect(addr, reg_offset, data, mask, false);
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}
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/* It is only used for USB3 direct access not on comphy lane2. */
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static void comphy_usb3_set_direct(uintptr_t addr, uint32_t reg_offset,
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uint16_t data, uint16_t mask, int mode)
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uint16_t data, uint16_t mask)
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{
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reg_set16((reg_offset * PHY_SHFT(USB3) + addr), data, mask);
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}
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@ -279,7 +291,6 @@ static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index,
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int ret = 0;
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uint32_t offset, data = 0, ref_clk;
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uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG;
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int mode = COMPHY_GET_MODE(comphy_mode);
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int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode);
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debug_enter();
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@ -289,8 +300,7 @@ static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index,
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/* Clear phy isolation mode to make it work in normal mode */
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offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
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comphy_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE,
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mode);
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comphy_sata_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE);
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/* 0. Check the Polarity invert bits */
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if (invert & COMPHY_POLARITY_TXD_INVERT)
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@ -299,13 +309,13 @@ static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index,
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data |= RXD_INVERT_BIT;
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offset = COMPHY_SYNC_PATTERN_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
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comphy_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT |
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RXD_INVERT_BIT, mode);
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comphy_sata_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT |
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RXD_INVERT_BIT);
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/* 1. Select 40-bit data width width */
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offset = COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET;
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comphy_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT,
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SEL_DATA_WIDTH_MASK, mode);
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comphy_sata_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT,
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SEL_DATA_WIDTH_MASK);
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/* 2. Select reference clock(25M) and PHY mode (SATA) */
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offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
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@ -314,17 +324,17 @@ static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index,
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else
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ref_clk = REF_CLOCK_SPEED_25M;
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comphy_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA,
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REF_FREF_SEL_MASK | PHY_MODE_MASK, mode);
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comphy_sata_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA,
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REF_FREF_SEL_MASK | PHY_MODE_MASK);
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/* 3. Use maximum PLL rate (no power save) */
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offset = COMPHY_KVCO_CAL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
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comphy_set_indirect(comphy_indir_regs, offset, USE_MAX_PLL_RATE_BIT,
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USE_MAX_PLL_RATE_BIT, mode);
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comphy_sata_set_indirect(comphy_indir_regs, offset, USE_MAX_PLL_RATE_BIT,
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USE_MAX_PLL_RATE_BIT);
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/* 4. Reset reserved bit */
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comphy_set_indirect(comphy_indir_regs, COMPHY_RESERVED_REG, 0,
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PHYCTRL_FRM_PIN_BIT, mode);
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comphy_sata_set_indirect(comphy_indir_regs, COMPHY_RESERVED_REG, 0,
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PHYCTRL_FRM_PIN_BIT);
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/* 5. Set vendor-specific configuration (It is done in sata driver) */
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/* XXX: in U-Boot below sequence was executed in this place, in Linux
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@ -589,8 +599,7 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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uintptr_t reg_base = 0;
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uint32_t mask, data, addr, cfg, ref_clk;
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void (*usb3_reg_set)(uintptr_t addr, uint32_t reg_offset, uint16_t data,
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uint16_t mask, int mode);
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int mode = COMPHY_GET_MODE(comphy_mode);
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uint16_t mask);
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int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode);
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debug_enter();
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@ -600,7 +609,7 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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/* Set usb3 reg access func, Lane2 is indirect access */
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if (comphy_index == COMPHY_LANE2) {
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usb3_reg_set = &comphy_set_indirect;
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usb3_reg_set = &comphy_usb3_set_indirect;
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reg_base = COMPHY_INDIRECT_REG;
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} else {
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/* Get the direct access register resource and map */
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@ -619,7 +628,7 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK |
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CFG_TX_ALIGN_POS_MASK;
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usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK,
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mask, mode);
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mask);
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/*
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* 2. Set BIT0: enable transmitter in high impedance mode
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@ -631,20 +640,20 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK |
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TX_ELEC_IDLE_MODE_EN;
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data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN;
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usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask, mode);
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usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask);
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/*
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* 3. Set Spread Spectrum Clock Enabled
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*/
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usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG4_ADDR,
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SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN, mode);
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SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN);
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/*
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* 4. Set Override Margining Controls From the MAC:
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* Use margining signals from lane configuration
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*/
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usb3_reg_set(reg_base, COMPHY_REG_TEST_MODE_CTRL_ADDR,
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MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK, mode);
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MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK);
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/*
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* 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles
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@ -652,13 +661,13 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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*/
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usb3_reg_set(reg_base, COMPHY_REG_GLOB_CLK_SRC_LO_ADDR, 0x0,
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(MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE |
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BUNDLE_SAMPLE_CTRL | PLL_READY_DLY), mode);
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BUNDLE_SAMPLE_CTRL | PLL_READY_DLY));
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/*
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* 6. Set G2 Spread Spectrum Clock Amplitude at 4K
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*/
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usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_2,
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G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK, mode);
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G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK);
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/*
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* 7. Unset G3 Spread Spectrum Clock Amplitude
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@ -667,7 +676,7 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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mask = G3_TX_SSC_AMP_MASK | G3_VREG_RXTX_MAS_ISET_MASK |
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RSVD_PH03FH_6_0_MASK;
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usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_3,
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G3_VREG_RXTX_MAS_ISET_60U, mask, mode);
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G3_VREG_RXTX_MAS_ISET_60U, mask);
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/*
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* 8. Check crystal jumper setting and program the Power and PLL Control
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@ -688,39 +697,37 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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REF_FREF_SEL_MASK;
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data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
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PU_TX_INTP_BIT | PU_DFE_BIT | PHY_MODE_USB3 | ref_clk;
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usb3_reg_set(reg_base, COMPHY_POWER_PLL_CTRL, data, mask, mode);
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usb3_reg_set(reg_base, COMPHY_POWER_PLL_CTRL, data, mask);
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mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |
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CFG_PM_RXDLOZ_WAIT_MASK;
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data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg;
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usb3_reg_set(reg_base, COMPHY_REG_PWR_MGM_TIM1_ADDR, data, mask, mode);
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usb3_reg_set(reg_base, COMPHY_REG_PWR_MGM_TIM1_ADDR, data, mask);
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/*
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* 9. Enable idle sync
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*/
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data = UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN;
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usb3_reg_set(reg_base, COMPHY_REG_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK,
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mode);
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usb3_reg_set(reg_base, COMPHY_REG_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK);
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/*
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* 10. Enable the output of 500M clock
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*/
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data = MISC_REG0_DEFAULT_VALUE | CLK500M_EN;
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usb3_reg_set(reg_base, COMPHY_MISC_REG0_ADDR, data, REG_16_BIT_MASK,
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mode);
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usb3_reg_set(reg_base, COMPHY_MISC_REG0_ADDR, data, REG_16_BIT_MASK);
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/*
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* 11. Set 20-bit data width
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*/
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usb3_reg_set(reg_base, COMPHY_LOOPBACK_REG0, DATA_WIDTH_20BIT,
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REG_16_BIT_MASK, mode);
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REG_16_BIT_MASK);
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/*
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* 12. Override Speed_PLL value and use MAC PLL
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*/
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usb3_reg_set(reg_base, COMPHY_KVCO_CAL_CTRL,
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(SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT),
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REG_16_BIT_MASK, mode);
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REG_16_BIT_MASK);
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/*
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* 13. Check the Polarity invert bit
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@ -733,27 +740,26 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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data |= RXD_INVERT_BIT;
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}
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mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
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usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, data, mask, mode);
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usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, data, mask);
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/*
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* 14. Set max speed generation to USB3.0 5Gbps
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*/
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usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN_REG, PHY_GEN_USB3_5G,
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PHY_GEN_MAX_MASK, mode);
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PHY_GEN_MAX_MASK);
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/*
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* 15. Set capacitor value for FFE gain peaking to 0xF
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*/
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usb3_reg_set(reg_base, COMPHY_REG_GEN3_SETTINGS_3,
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COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK,
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mode);
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COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK);
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/*
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* 16. Release SW reset
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*/
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data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4;
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usb3_reg_set(reg_base, COMPHY_REG_GLOB_PHY_CTRL0_ADDR, data,
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REG_16_BIT_MASK, mode);
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REG_16_BIT_MASK);
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/* Wait for > 55 us to allow PCLK be enabled */
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udelay(PLL_SET_DELAY_US);
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@ -928,13 +934,13 @@ static int mvebu_a3700_comphy_sata_power_off(void)
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/* Set phy isolation mode */
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offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
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comphy_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE,
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PHY_ISOLATE_MODE, COMPHY_SATA_MODE);
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comphy_sata_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE,
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PHY_ISOLATE_MODE);
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/* Power off PLL, Tx, Rx */
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offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
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comphy_set_indirect(comphy_indir_regs, offset, 0,
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PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT, COMPHY_SATA_MODE);
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comphy_sata_set_indirect(comphy_indir_regs, offset, 0,
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PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT);
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debug_exit();
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