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Merge "feat(plat/versal): add support for SLS mitigation" into integration

This commit is contained in:
Madhukar Pappireddy 2021-08-13 17:22:12 +02:00 committed by TrustedFirmware Code Review
parent d6449d2927 302b4dfb8f
commit be3a51ce18
2 changed files with 10 additions and 0 deletions
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5
docs/plat/xilinx-versal.rst
View File

@ -24,6 +24,11 @@ To build TF-A for JTAG DCC console
make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal bl31 VERSAL_CONSOLE=dcc
```
To build TF-A with Straight-Line Speculation(SLS)
```bash
make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal bl31 HARDEN_SLS_ALL=1
```
Xilinx Versal platform specific build options
---------------------------------------------

5
plat/xilinx/versal/platform.mk
View File

@ -9,6 +9,7 @@ SEPARATE_CODE_AND_RODATA := 1
override RESET_TO_BL31 := 1
PL011_GENERIC_UART := 1
IPI_CRC_CHECK := 0
HARDEN_SLS_ALL := 0
ifdef VERSAL_ATF_MEM_BASE
$(eval $(call add_define,VERSAL_ATF_MEM_BASE))
@ -87,3 +88,7 @@ BL31_SOURCES += drivers/arm/cci/cci.c \
plat/xilinx/versal/pm_service/pm_svc_main.c \
plat/xilinx/versal/pm_service/pm_api_sys.c \
plat/xilinx/versal/pm_service/pm_client.c
ifeq ($(HARDEN_SLS_ALL), 1)
TF_CFLAGS_aarch64 += -mharden-sls=all
endif