Merge "feat(plat/versal): add support for SLS mitigation" into integration
This commit is contained in:
commit
be3a51ce18
|
@ -24,6 +24,11 @@ To build TF-A for JTAG DCC console
|
||||||
make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal bl31 VERSAL_CONSOLE=dcc
|
make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal bl31 VERSAL_CONSOLE=dcc
|
||||||
```
|
```
|
||||||
|
|
||||||
|
To build TF-A with Straight-Line Speculation(SLS)
|
||||||
|
```bash
|
||||||
|
make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal bl31 HARDEN_SLS_ALL=1
|
||||||
|
```
|
||||||
|
|
||||||
Xilinx Versal platform specific build options
|
Xilinx Versal platform specific build options
|
||||||
---------------------------------------------
|
---------------------------------------------
|
||||||
|
|
||||||
|
|
|
@ -9,6 +9,7 @@ SEPARATE_CODE_AND_RODATA := 1
|
||||||
override RESET_TO_BL31 := 1
|
override RESET_TO_BL31 := 1
|
||||||
PL011_GENERIC_UART := 1
|
PL011_GENERIC_UART := 1
|
||||||
IPI_CRC_CHECK := 0
|
IPI_CRC_CHECK := 0
|
||||||
|
HARDEN_SLS_ALL := 0
|
||||||
|
|
||||||
ifdef VERSAL_ATF_MEM_BASE
|
ifdef VERSAL_ATF_MEM_BASE
|
||||||
$(eval $(call add_define,VERSAL_ATF_MEM_BASE))
|
$(eval $(call add_define,VERSAL_ATF_MEM_BASE))
|
||||||
|
@ -87,3 +88,7 @@ BL31_SOURCES += drivers/arm/cci/cci.c \
|
||||||
plat/xilinx/versal/pm_service/pm_svc_main.c \
|
plat/xilinx/versal/pm_service/pm_svc_main.c \
|
||||||
plat/xilinx/versal/pm_service/pm_api_sys.c \
|
plat/xilinx/versal/pm_service/pm_api_sys.c \
|
||||||
plat/xilinx/versal/pm_service/pm_client.c
|
plat/xilinx/versal/pm_service/pm_client.c
|
||||||
|
|
||||||
|
ifeq ($(HARDEN_SLS_ALL), 1)
|
||||||
|
TF_CFLAGS_aarch64 += -mharden-sls=all
|
||||||
|
endif
|
||||||
|
|
Loading…
Reference in New Issue