rcar_gen3: drivers: qos: M3N: Configure DBSC QoS from a table
Convert the DBSC QoS setting function to a simple table of register-value pairs and pass it to common rcar_qos_dbsc_setting() to write those values to matching registers. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I46b445a77b39412e7a41ae0e0e087a409d0c22e3
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@ -58,54 +58,47 @@
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#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
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#endif
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static void dbsc_setting(void)
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{
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/* Register write enable */
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io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
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struct rcar_gen3_dbsc_qos_settings m3n_v10_qos[] = {
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/* BUFCAM settings */
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io_write_32(DBSC_DBCAM0CNF1, 0x00043218);
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io_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
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io_write_32(DBSC_DBSCHCNT0, 0x000F0037);
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io_write_32(DBSC_DBSCHSZ0, 0x00000001);
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io_write_32(DBSC_DBSCHRW0, 0x22421111);
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{ DBSC_DBCAM0CNF1, 0x00043218 },
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{ DBSC_DBCAM0CNF2, 0x000000F4 },
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{ DBSC_DBSCHCNT0, 0x000F0037 },
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{ DBSC_DBSCHSZ0, 0x00000001 },
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{ DBSC_DBSCHRW0, 0x22421111 },
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/* DDR3 */
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io_write_32(DBSC_SCFCTST2, 0x012F1123);
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{ DBSC_SCFCTST2, 0x012F1123 },
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/* QoS Settings */
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io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
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io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
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io_write_32(DBSC_DBSCHQOS02, 0x00000000);
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io_write_32(DBSC_DBSCHQOS03, 0x00000000);
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io_write_32(DBSC_DBSCHQOS40, 0x00000300);
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io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
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io_write_32(DBSC_DBSCHQOS42, 0x00000200);
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io_write_32(DBSC_DBSCHQOS43, 0x00000100);
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io_write_32(DBSC_DBSCHQOS90, 0x00000100);
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io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
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io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
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io_write_32(DBSC_DBSCHQOS93, 0x00000040);
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io_write_32(DBSC_DBSCHQOS130, 0x00000100);
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io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
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io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
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io_write_32(DBSC_DBSCHQOS133, 0x00000040);
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io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
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io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
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io_write_32(DBSC_DBSCHQOS142, 0x00000080);
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io_write_32(DBSC_DBSCHQOS143, 0x00000040);
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io_write_32(DBSC_DBSCHQOS150, 0x00000040);
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io_write_32(DBSC_DBSCHQOS151, 0x00000030);
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io_write_32(DBSC_DBSCHQOS152, 0x00000020);
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io_write_32(DBSC_DBSCHQOS153, 0x00000010);
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/* Register write protect */
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io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
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}
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{ DBSC_DBSCHQOS00, 0x00000F00 },
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{ DBSC_DBSCHQOS01, 0x00000B00 },
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{ DBSC_DBSCHQOS02, 0x00000000 },
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{ DBSC_DBSCHQOS03, 0x00000000 },
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{ DBSC_DBSCHQOS40, 0x00000300 },
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{ DBSC_DBSCHQOS41, 0x000002F0 },
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{ DBSC_DBSCHQOS42, 0x00000200 },
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{ DBSC_DBSCHQOS43, 0x00000100 },
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{ DBSC_DBSCHQOS90, 0x00000100 },
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{ DBSC_DBSCHQOS91, 0x000000F0 },
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{ DBSC_DBSCHQOS92, 0x000000A0 },
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{ DBSC_DBSCHQOS93, 0x00000040 },
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{ DBSC_DBSCHQOS130, 0x00000100 },
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{ DBSC_DBSCHQOS131, 0x000000F0 },
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{ DBSC_DBSCHQOS132, 0x000000A0 },
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{ DBSC_DBSCHQOS133, 0x00000040 },
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{ DBSC_DBSCHQOS140, 0x000000C0 },
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{ DBSC_DBSCHQOS141, 0x000000B0 },
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{ DBSC_DBSCHQOS142, 0x00000080 },
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{ DBSC_DBSCHQOS143, 0x00000040 },
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{ DBSC_DBSCHQOS150, 0x00000040 },
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{ DBSC_DBSCHQOS151, 0x00000030 },
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{ DBSC_DBSCHQOS152, 0x00000020 },
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{ DBSC_DBSCHQOS153, 0x00000010 },
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};
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void qos_init_m3n_v10(void)
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{
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dbsc_setting();
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rcar_qos_dbsc_setting(m3n_v10_qos, ARRAY_SIZE(m3n_v10_qos), true);
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/* DRAM Split Address mapping */
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#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
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