Merge pull request #853 from vwadekar/tegra-changes-from-downstream-v3
Tegra changes from downstream v3
This commit is contained in:
davidcunado-arm
GitHub
commit
bea7caff8d
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@ -84,3 +84,10 @@ The PSCI implementation expects each platform to expose the 'power state'
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parameter to be used during the 'SYSTEM SUSPEND' call. The state-id field
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is implementation defined on Tegra SoCs and is preferably defined by
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tegra_def.h.
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Tegra configs
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=============
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* 'tegra_enable_l2_ecc_parity_prot': This flag enables the L2 ECC and Parity
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Protection bit, for ARM Cortex-A57 CPUs, during CPU boot. This flag will
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be enabled by Tegrs SoCs during 'Cluster power up' or 'System Suspend' exit.
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@ -87,6 +87,8 @@
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#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2
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#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2
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#define L2_ECC_PARITY_PROTECTION_BIT (1 << 21)
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/*******************************************************************************
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* L2 Extended Control register specific definitions.
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******************************************************************************/
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@ -52,6 +52,7 @@ __BEGIN_DECLS
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void *memchr(const void *, int, size_t) __pure;
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int memcmp(const void *, const void *, size_t) __pure;
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void *memcpy(void * __restrict, const void * __restrict, size_t);
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void *memcpy16(void * __restrict, const void * __restrict, size_t);
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void *memmove(void *, const void *, size_t);
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void *memset(void *, int, size_t);
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@ -59,7 +59,6 @@ func denver_enable_dco
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mov x1, #1
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lsl x1, x1, x0
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msr s3_0_c15_c0_2, x1
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isb
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ret
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endfunc denver_enable_dco
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@ -33,6 +33,7 @@
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#include <cpu_macros.S>
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#include <cortex_a57.h>
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#include <cortex_a53.h>
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#include <platform_def.h>
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#include <tegra_def.h>
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#define MIDR_PN_CORTEX_A57 0xD07
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@ -67,6 +68,7 @@
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.globl ns_image_entrypoint
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.globl tegra_bl31_phys_base
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.globl tegra_console_base
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.globl tegra_enable_l2_ecc_parity_prot
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/* ---------------------
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* Common CPU init code
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@ -75,8 +77,8 @@
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.macro cpu_init_common
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/* ------------------------------------------------
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* We enable procesor retention and L2/CPUECTLR NS
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* access for A57 CPUs only.
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* We enable procesor retention, L2/CPUECTLR NS
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* access and ECC/Parity protection for A57 CPUs
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* ------------------------------------------------
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*/
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mrs x0, midr_el1
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@ -89,7 +91,7 @@
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/* ---------------------------
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* Enable processor retention
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* ---------------------------
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*/
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*/
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mrs x0, L2ECTLR_EL1
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mov x1, #RETENTION_ENTRY_TICKS_512 << L2ECTLR_RET_CTRL_SHIFT
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bic x0, x0, #L2ECTLR_RET_CTRL_MASK
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@ -107,12 +109,26 @@
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/* -------------------------------------------------------
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* Enable L2 and CPU ECTLR RW access from non-secure world
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* -------------------------------------------------------
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*/
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*/
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mov x0, #ACTLR_EL3_ENABLE_ALL_ACCESS
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msr actlr_el3, x0
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msr actlr_el2, x0
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isb
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/* -------------------------------------------------------
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* Enable L2 ECC and Parity Protection
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* -------------------------------------------------------
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*/
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adr x0, tegra_enable_l2_ecc_parity_prot
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ldr x0, [x0]
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cbz x0, 1f
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mrs x0, L2CTLR_EL1
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and x1, x0, #L2_ECC_PARITY_PROTECTION_BIT
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cbnz x1, 1f
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orr x0, x0, #L2_ECC_PARITY_PROTECTION_BIT
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msr L2CTLR_EL1, x0
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isb
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/* --------------------------------
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* Enable the cycle count register
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* --------------------------------
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@ -254,6 +270,47 @@ endfunc plat_crash_console_putc
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*/
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func plat_reset_handler
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/* ----------------------------------------------------
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* Verify if we are running from BL31_BASE address
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* ----------------------------------------------------
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*/
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adr x18, bl31_entrypoint
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mov x17, #BL31_BASE
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cmp x18, x17
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b.eq 1f
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/* ----------------------------------------------------
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* Copy the entire BL31 code to BL31_BASE if we are not
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* running from it already
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* ----------------------------------------------------
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*/
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mov x0, x17
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mov x1, x18
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mov x2, #BL31_SIZE
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_loop16:
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cmp x2, #16
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b.lt _loop1
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ldp x3, x4, [x1], #16
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stp x3, x4, [x0], #16
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sub x2, x2, #16
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b _loop16
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/* copy byte per byte */
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_loop1:
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cbz x2, _end
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ldrb w3, [x1], #1
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strb w3, [x0], #1
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subs x2, x2, #1
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b.ne _loop1
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/* ----------------------------------------------------
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* Jump to BL31_BASE and start execution again
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* ----------------------------------------------------
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*/
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_end: mov x0, x20
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mov x1, x21
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br x17
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1:
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/* -----------------------------------
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* derive and save the phys_base addr
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* -----------------------------------
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@ -412,3 +469,10 @@ tegra_bl31_phys_base:
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*/
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tegra_console_base:
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.quad 0
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/* --------------------------------------------------
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* Enable L2 ECC and Parity Protection
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* --------------------------------------------------
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*/
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tegra_enable_l2_ecc_parity_prot:
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.quad 0
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@ -44,9 +44,12 @@
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#include <platform.h>
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#include <platform_def.h>
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#include <stddef.h>
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#include <string.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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extern void zeromem16(void *mem, unsigned int length);
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/*******************************************************************************
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* Declarations of linker defined symbols which will help us find the layout
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* of trusted SRAM
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@ -79,6 +82,29 @@ static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
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******************************************************************************/
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extern uint64_t ns_image_entrypoint;
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/*******************************************************************************
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* The following platform setup functions are weakly defined. They
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* provide typical implementations that will be overridden by a SoC.
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******************************************************************************/
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#pragma weak plat_early_platform_setup
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#pragma weak plat_get_bl31_params
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#pragma weak plat_get_bl31_plat_params
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void plat_early_platform_setup(void)
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{
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; /* do nothing */
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}
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bl31_params_t *plat_get_bl31_params(void)
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{
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return NULL;
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}
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plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
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{
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return NULL;
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}
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image for
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* security state specified. BL33 corresponds to the non-secure image type
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@ -89,7 +115,8 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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if (type == NON_SECURE)
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return &bl33_image_ep_info;
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if (type == SECURE)
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/* return BL32 entry point info if it is valid */
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if (type == SECURE && bl32_image_ep_info.pc)
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return &bl32_image_ep_info;
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return NULL;
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@ -116,11 +143,25 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
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#if DEBUG
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int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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#endif
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image_info_t bl32_img_info = { {0} };
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uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
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/*
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* For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
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* there's no argument to relay from a previous bootloader. Platforms
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* might use custom ways to get arguments, so provide handlers which
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* they can override.
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*/
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if (from_bl2 == NULL)
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from_bl2 = plat_get_bl31_params();
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if (plat_params == NULL)
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plat_params = plat_get_bl31_plat_params();
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/*
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* Copy BL3-3, BL3-2 entry point information.
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* They are stored in Secure RAM, in BL2's address space.
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*/
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assert(from_bl2);
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assert(from_bl2->bl33_ep_info);
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bl33_image_ep_info = *from_bl2->bl33_ep_info;
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@ -135,6 +176,14 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
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plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
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plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
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/*
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* It is very important that we run either from TZDRAM or TZSRAM base.
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* Add an explicit check here.
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*/
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if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) &&
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(TEGRA_TZRAM_BASE != BL31_BASE))
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panic();
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/*
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* Get the base address of the UART controller to be used for the
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* console
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@ -152,6 +201,51 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
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/* Initialise crash console */
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plat_crash_console_init();
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/*
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* Do initial security configuration to allow DRAM/device access.
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*/
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tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
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plat_bl31_params_from_bl2.tzdram_size);
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/*
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* The previous bootloader might not have placed the BL32 image
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* inside the TZDRAM. We check the BL32 image info to find out
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* the base/PC values and relocate the image if necessary.
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*/
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if (from_bl2->bl32_image_info) {
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bl32_img_info = *from_bl2->bl32_image_info;
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/* Relocate BL32 if it resides outside of the TZDRAM */
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tzdram_start = plat_bl31_params_from_bl2.tzdram_base;
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tzdram_end = plat_bl31_params_from_bl2.tzdram_base +
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plat_bl31_params_from_bl2.tzdram_size;
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bl32_start = bl32_img_info.image_base;
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bl32_end = bl32_img_info.image_base + bl32_img_info.image_size;
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assert(tzdram_end > tzdram_start);
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assert(bl32_end > bl32_start);
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assert(bl32_image_ep_info.pc > tzdram_start);
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assert(bl32_image_ep_info.pc < tzdram_end);
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/* relocate BL32 */
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if (bl32_start >= tzdram_end || bl32_end <= tzdram_start) {
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INFO("Relocate BL32 to TZDRAM\n");
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memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc,
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(void *)(uintptr_t)bl32_start,
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bl32_img_info.image_size);
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/* clean up non-secure intermediate buffer */
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zeromem16((void *)(uintptr_t)bl32_start,
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bl32_img_info.image_size);
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}
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}
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/* Early platform setup for Tegra SoCs */
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plat_early_platform_setup();
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INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ?
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"Denver" : "ARM", read_mpidr());
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}
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@ -163,6 +257,9 @@ void bl31_platform_setup(void)
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{
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uint32_t tmp_reg;
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/* Initialize the gic cpu and distributor interfaces */
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plat_gic_setup();
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/*
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* Initialize delay timer
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*/
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@ -178,12 +275,6 @@ void bl31_platform_setup(void)
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*/
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tegra_memctrl_setup();
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/*
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* Do initial security configuration to allow DRAM/device access.
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*/
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tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
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plat_bl31_params_from_bl2.tzdram_size);
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/*
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* Set up the TZRAM memory aperture to allow only secure world
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* access
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@ -194,9 +285,6 @@ void bl31_platform_setup(void)
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tmp_reg = SCR_RES1_BITS | SCR_RW_BIT;
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write_scr(tmp_reg);
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/* Initialize the gic cpu and distributor interfaces */
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tegra_gic_setup();
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INFO("BL3-1: Tegra platform setup complete\n");
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}
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@ -47,16 +47,15 @@ PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
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COMMON_DIR := plat/nvidia/tegra/common
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BL31_SOURCES += drivers/arm/gic/gic_v2.c \
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drivers/arm/gic/gic_v3.c \
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drivers/console/aarch64/console.S \
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drivers/delay_timer/delay_timer.c \
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drivers/ti/uart/aarch64/16550_console.S \
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plat/common/aarch64/platform_mp_stack.S \
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plat/common/plat_psci_common.c \
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${COMMON_DIR}/aarch64/tegra_helpers.S \
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${COMMON_DIR}/drivers/pmc/pmc.c \
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${COMMON_DIR}/tegra_bl31_setup.c \
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${COMMON_DIR}/tegra_delay_timer.c \
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${COMMON_DIR}/tegra_fiq_glue.c \
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${COMMON_DIR}/tegra_gic.c \
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${COMMON_DIR}/tegra_pm.c \
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${COMMON_DIR}/tegra_sip_calls.c \
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@ -0,0 +1,162 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are met:
|
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*
|
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* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
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*
|
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* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
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*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bakery_lock.h>
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#include <bl_common.h>
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#include <context.h>
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#include <context_mgmt.h>
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#include <debug.h>
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#include <denver.h>
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#include <gic_v2.h>
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#include <interrupt_mgmt.h>
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#include <platform.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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DEFINE_BAKERY_LOCK(tegra_fiq_lock);
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|
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/*******************************************************************************
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* Static variables
|
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******************************************************************************/
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static uint64_t ns_fiq_handler_addr;
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static unsigned int fiq_handler_active;
|
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static pcpu_fiq_state_t fiq_state[PLATFORM_CORE_COUNT];
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/*******************************************************************************
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* Handler for FIQ interrupts
|
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******************************************************************************/
|
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static uint64_t tegra_fiq_interrupt_handler(uint32_t id,
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uint32_t flags,
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void *handle,
|
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void *cookie)
|
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{
|
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cpu_context_t *ctx = cm_get_context(NON_SECURE);
|
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el3_state_t *el3state_ctx = get_el3state_ctx(ctx);
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int cpu = plat_my_core_pos();
|
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uint32_t irq;
|
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|
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bakery_lock_get(&tegra_fiq_lock);
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|
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/*
|
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* The FIQ was generated when the execution was in the non-secure
|
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* world. Save the context registers to start with.
|
||||
*/
|
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cm_el1_sysregs_context_save(NON_SECURE);
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|
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/*
|
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* Save elr_el3 and spsr_el3 from the saved context, and overwrite
|
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* the context with the NS fiq_handler_addr and SPSR value.
|
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*/
|
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fiq_state[cpu].elr_el3 = read_ctx_reg(el3state_ctx, CTX_ELR_EL3);
|
||||
fiq_state[cpu].spsr_el3 = read_ctx_reg(el3state_ctx, CTX_SPSR_EL3);
|
||||
|
||||
/*
|
||||
* Set the new ELR to continue execution in the NS world using the
|
||||
* FIQ handler registered earlier.
|
||||
*/
|
||||
assert(ns_fiq_handler_addr);
|
||||
write_ctx_reg(el3state_ctx, CTX_ELR_EL3, ns_fiq_handler_addr);
|
||||
|
||||
/*
|
||||
* Mark this interrupt as complete to avoid a FIQ storm.
|
||||
*/
|
||||
irq = plat_ic_acknowledge_interrupt();
|
||||
if (irq < 1022)
|
||||
plat_ic_end_of_interrupt(irq);
|
||||
|
||||
bakery_lock_release(&tegra_fiq_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Setup handler for FIQ interrupts
|
||||
******************************************************************************/
|
||||
void tegra_fiq_handler_setup(void)
|
||||
{
|
||||
uint64_t flags;
|
||||
int rc;
|
||||
|
||||
/* return if already registered */
|
||||
if (fiq_handler_active)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Register an interrupt handler for FIQ interrupts generated for
|
||||
* NS interrupt sources
|
||||
*/
|
||||
flags = 0;
|
||||
set_interrupt_rm_flag(flags, NON_SECURE);
|
||||
rc = register_interrupt_type_handler(INTR_TYPE_EL3,
|
||||
tegra_fiq_interrupt_handler,
|
||||
flags);
|
||||
if (rc)
|
||||
panic();
|
||||
|
||||
/* handler is now active */
|
||||
fiq_handler_active = 1;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Validate and store NS world's entrypoint for FIQ interrupts
|
||||
******************************************************************************/
|
||||
void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint)
|
||||
{
|
||||
ns_fiq_handler_addr = entrypoint;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Handler to return the NS EL1/EL0 CPU context
|
||||
******************************************************************************/
|
||||
int tegra_fiq_get_intr_context(void)
|
||||
{
|
||||
cpu_context_t *ctx = cm_get_context(NON_SECURE);
|
||||
gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx);
|
||||
el1_sys_regs_t *el1state_ctx = get_sysregs_ctx(ctx);
|
||||
int cpu = plat_my_core_pos();
|
||||
uint64_t val;
|
||||
|
||||
/*
|
||||
* We store the ELR_EL3, SPSR_EL3, SP_EL0 and SP_EL1 registers so
|
||||
* that el3_exit() sends these values back to the NS world.
|
||||
*/
|
||||
write_ctx_reg(gpregs_ctx, CTX_GPREG_X0, fiq_state[cpu].elr_el3);
|
||||
write_ctx_reg(gpregs_ctx, CTX_GPREG_X1, fiq_state[cpu].spsr_el3);
|
||||
|
||||
val = read_ctx_reg(gpregs_ctx, CTX_GPREG_SP_EL0);
|
||||
write_ctx_reg(gpregs_ctx, CTX_GPREG_X2, val);
|
||||
|
||||
val = read_ctx_reg(el1state_ctx, CTX_SP_EL1);
|
||||
write_ctx_reg(gpregs_ctx, CTX_GPREG_X3, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -47,6 +47,9 @@
|
|||
(GIC_HIGHEST_NS_PRIORITY << 16) | \
|
||||
(GIC_HIGHEST_NS_PRIORITY << 24))
|
||||
|
||||
static const irq_sec_cfg_t *g_irq_sec_ptr;
|
||||
static unsigned int g_num_irqs;
|
||||
|
||||
/*******************************************************************************
|
||||
* Place the cpu interface in a state where it can never make a cpu exit wfi as
|
||||
* as result of an asserted interrupt. This is critical for powering down a cpu
|
||||
|
|
@ -110,7 +113,9 @@ static void tegra_gic_pcpu_distif_setup(unsigned int gicd_base)
|
|||
******************************************************************************/
|
||||
static void tegra_gic_distif_setup(unsigned int gicd_base)
|
||||
{
|
||||
unsigned int index, num_ints;
|
||||
unsigned int index, num_ints, irq_num;
|
||||
uint8_t target_cpus;
|
||||
uint32_t val;
|
||||
|
||||
/*
|
||||
* Mark out non-secure interrupts. Calculate number of
|
||||
|
|
@ -128,6 +133,39 @@ static void tegra_gic_distif_setup(unsigned int gicd_base)
|
|||
GICD_IPRIORITYR_DEF_VAL);
|
||||
}
|
||||
|
||||
/* Configure SPI secure interrupts now */
|
||||
if (g_irq_sec_ptr) {
|
||||
|
||||
for (index = 0; index < g_num_irqs; index++) {
|
||||
irq_num = (g_irq_sec_ptr + index)->irq;
|
||||
target_cpus = (g_irq_sec_ptr + index)->target_cpus;
|
||||
|
||||
if (irq_num >= MIN_SPI_ID) {
|
||||
|
||||
/* Configure as a secure interrupt */
|
||||
gicd_clr_igroupr(gicd_base, irq_num);
|
||||
|
||||
/* Configure SPI priority */
|
||||
mmio_write_8(gicd_base + GICD_IPRIORITYR +
|
||||
irq_num,
|
||||
GIC_HIGHEST_SEC_PRIORITY &
|
||||
GIC_PRI_MASK);
|
||||
|
||||
/* Configure as level triggered */
|
||||
val = gicd_read_icfgr(gicd_base, irq_num);
|
||||
val |= (3 << ((irq_num & 0xF) << 1));
|
||||
gicd_write_icfgr(gicd_base, irq_num, val);
|
||||
|
||||
/* Route SPI to the target CPUs */
|
||||
gicd_set_itargetsr(gicd_base, irq_num,
|
||||
target_cpus);
|
||||
|
||||
/* Enable this interrupt */
|
||||
gicd_set_isenabler(gicd_base, irq_num);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Configure the SGI and PPI. This is done in a separated function
|
||||
* because each CPU is responsible for initializing its own private
|
||||
|
|
@ -139,8 +177,11 @@ static void tegra_gic_distif_setup(unsigned int gicd_base)
|
|||
gicd_write_ctlr(gicd_base, ENABLE_GRP0 | ENABLE_GRP1);
|
||||
}
|
||||
|
||||
void tegra_gic_setup(void)
|
||||
void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, unsigned int num_irqs)
|
||||
{
|
||||
g_irq_sec_ptr = irq_sec_ptr;
|
||||
g_num_irqs = num_irqs;
|
||||
|
||||
tegra_gic_cpuif_setup(TEGRA_GICC_BASE);
|
||||
tegra_gic_distif_setup(TEGRA_GICD_BASE);
|
||||
}
|
||||
|
|
@ -185,12 +226,17 @@ uint32_t tegra_gic_interrupt_type_to_line(uint32_t type,
|
|||
uint32_t tegra_gic_get_pending_interrupt_type(void)
|
||||
{
|
||||
uint32_t id;
|
||||
unsigned int index;
|
||||
|
||||
id = gicc_read_hppir(TEGRA_GICC_BASE) & INT_ID_MASK;
|
||||
|
||||
/* Assume that all secure interrupts are S-EL1 interrupts */
|
||||
if (id < 1022)
|
||||
return INTR_TYPE_S_EL1;
|
||||
/* get the interrupt type */
|
||||
if (id < 1022) {
|
||||
for (index = 0; index < g_num_irqs; index++) {
|
||||
if (id == (g_irq_sec_ptr + index)->irq)
|
||||
return (g_irq_sec_ptr + index)->type;
|
||||
}
|
||||
}
|
||||
|
||||
if (id == GIC_SPURIOUS_INTERRUPT)
|
||||
return INTR_TYPE_INVAL;
|
||||
|
|
@ -248,14 +294,19 @@ void tegra_gic_end_of_interrupt(uint32_t id)
|
|||
uint32_t tegra_gic_get_interrupt_type(uint32_t id)
|
||||
{
|
||||
uint32_t group;
|
||||
unsigned int index;
|
||||
|
||||
group = gicd_get_igroupr(TEGRA_GICD_BASE, id);
|
||||
|
||||
/* Assume that all secure interrupts are S-EL1 interrupts */
|
||||
if (group == GRP0)
|
||||
return INTR_TYPE_S_EL1;
|
||||
else
|
||||
return INTR_TYPE_NS;
|
||||
/* get the interrupt type */
|
||||
if (group == GRP0) {
|
||||
for (index = 0; index < g_num_irqs; index++) {
|
||||
if (id == (g_irq_sec_ptr + index)->irq)
|
||||
return (g_irq_sec_ptr + index)->type;
|
||||
}
|
||||
}
|
||||
|
||||
return INTR_TYPE_NS;
|
||||
}
|
||||
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -57,6 +57,7 @@ extern uint64_t tegra_sec_entry_point;
|
|||
#pragma weak tegra_soc_pwr_domain_power_down_wfi
|
||||
#pragma weak tegra_soc_prepare_system_reset
|
||||
#pragma weak tegra_soc_prepare_system_off
|
||||
#pragma weak tegra_soc_get_target_pwr_state
|
||||
|
||||
int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
|
||||
{
|
||||
|
|
@ -94,6 +95,23 @@ __dead2 void tegra_soc_prepare_system_off(void)
|
|||
panic();
|
||||
}
|
||||
|
||||
plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
|
||||
const plat_local_state_t *states,
|
||||
unsigned int ncpu)
|
||||
{
|
||||
plat_local_state_t target = PLAT_MAX_RET_STATE, temp;
|
||||
|
||||
assert(ncpu);
|
||||
|
||||
do {
|
||||
temp = *states++;
|
||||
if ((temp > target) && (temp != PLAT_MAX_OFF_STATE))
|
||||
target = temp;
|
||||
} while (--ncpu);
|
||||
|
||||
return target;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND`
|
||||
* call to get the `power_state` parameter. This allows the platform to encode
|
||||
|
|
@ -102,12 +120,9 @@ __dead2 void tegra_soc_prepare_system_off(void)
|
|||
******************************************************************************/
|
||||
void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state)
|
||||
{
|
||||
/* lower affinities use PLAT_MAX_OFF_STATE */
|
||||
for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
|
||||
req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
|
||||
|
||||
/* max affinity uses system suspend state id */
|
||||
req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PSTATE_ID_SOC_POWERDN;
|
||||
/* all affinities use system suspend state id */
|
||||
for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
|
||||
req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -183,7 +198,7 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
|||
/*
|
||||
* Initialize the GIC cpu and distributor interfaces
|
||||
*/
|
||||
tegra_gic_setup();
|
||||
plat_gic_setup();
|
||||
|
||||
/*
|
||||
* Check if we are exiting from deep sleep.
|
||||
|
|
@ -203,6 +218,12 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
|||
plat_params = bl31_get_plat_params();
|
||||
tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
|
||||
plat_params->tzdram_size);
|
||||
|
||||
/*
|
||||
* Set up the TZRAM memory aperture to allow only secure world
|
||||
* access
|
||||
*/
|
||||
tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -318,3 +339,14 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform handler to calculate the proper target power level at the
|
||||
* specified affinity level
|
||||
******************************************************************************/
|
||||
plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
|
||||
const plat_local_state_t *states,
|
||||
unsigned int ncpu)
|
||||
{
|
||||
return tegra_soc_get_target_pwr_state(lvl, states, ncpu);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -42,6 +42,8 @@
|
|||
* Common Tegra SiP SMCs
|
||||
******************************************************************************/
|
||||
#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
|
||||
#define TEGRA_SIP_FIQ_NS_ENTRYPOINT 0x82000005
|
||||
#define TEGRA_SIP_FIQ_NS_GET_CONTEXT 0x82000006
|
||||
|
||||
/*******************************************************************************
|
||||
* SoC specific SiP handler
|
||||
|
|
@ -60,7 +62,7 @@ int plat_sip_handler(uint32_t smc_fid,
|
|||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function is responsible for handling all SiP calls from the NS world
|
||||
* This function is responsible for handling all SiP calls
|
||||
******************************************************************************/
|
||||
uint64_t tegra_sip_handler(uint32_t smc_fid,
|
||||
uint64_t x1,
|
||||
|
|
@ -71,14 +73,8 @@ uint64_t tegra_sip_handler(uint32_t smc_fid,
|
|||
void *handle,
|
||||
uint64_t flags)
|
||||
{
|
||||
uint32_t ns;
|
||||
int err;
|
||||
|
||||
/* Determine which security state this SMC originated from */
|
||||
ns = is_caller_non_secure(flags);
|
||||
if (!ns)
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
|
||||
/* Check if this is a SoC specific SiP */
|
||||
err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
|
||||
if (err == 0)
|
||||
|
|
@ -114,6 +110,41 @@ uint64_t tegra_sip_handler(uint32_t smc_fid,
|
|||
SMC_RET1(handle, 0);
|
||||
break;
|
||||
|
||||
/*
|
||||
* The NS world registers the address of its handler to be
|
||||
* used for processing the FIQ. This is normally used by the
|
||||
* NS FIQ debugger driver to detect system hangs by programming
|
||||
* a watchdog timer to fire a FIQ interrupt.
|
||||
*/
|
||||
case TEGRA_SIP_FIQ_NS_ENTRYPOINT:
|
||||
|
||||
if (!x1)
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
|
||||
/*
|
||||
* TODO: Check if x1 contains a valid DRAM address
|
||||
*/
|
||||
|
||||
/* store the NS world's entrypoint */
|
||||
tegra_fiq_set_ns_entrypoint(x1);
|
||||
|
||||
SMC_RET1(handle, 0);
|
||||
break;
|
||||
|
||||
/*
|
||||
* The NS world's FIQ handler issues this SMC to get the NS EL1/EL0
|
||||
* CPU context when the FIQ interrupt was triggered. This allows the
|
||||
* NS world to understand the CPU state when the watchdog interrupt
|
||||
* triggered.
|
||||
*/
|
||||
case TEGRA_SIP_FIQ_NS_GET_CONTEXT:
|
||||
|
||||
/* retrieve context registers when FIQ triggered */
|
||||
tegra_fiq_get_intr_context();
|
||||
|
||||
SMC_RET0(handle);
|
||||
break;
|
||||
|
||||
default:
|
||||
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -42,6 +42,9 @@
|
|||
#define TEGRA_DRAM_BASE 0x80000000
|
||||
#define TEGRA_DRAM_END 0x27FFFFFFF
|
||||
|
||||
/*******************************************************************************
|
||||
* Struct for parameters received from BL2
|
||||
******************************************************************************/
|
||||
typedef struct plat_params_from_bl2 {
|
||||
/* TZ memory size */
|
||||
uint64_t tzdram_size;
|
||||
|
|
@ -51,6 +54,26 @@ typedef struct plat_params_from_bl2 {
|
|||
int uart_id;
|
||||
} plat_params_from_bl2_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Per-CPU struct describing FIQ state to be stored
|
||||
******************************************************************************/
|
||||
typedef struct pcpu_fiq_state {
|
||||
uint64_t elr_el3;
|
||||
uint64_t spsr_el3;
|
||||
} pcpu_fiq_state_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Struct describing per-FIQ configuration settings
|
||||
******************************************************************************/
|
||||
typedef struct irq_sec_cfg {
|
||||
/* IRQ number */
|
||||
unsigned int irq;
|
||||
/* Target CPUs servicing this interrupt */
|
||||
unsigned int target_cpus;
|
||||
/* type = INTR_TYPE_S_EL1 or INTR_TYPE_EL3 */
|
||||
uint32_t type;
|
||||
} irq_sec_cfg_t;
|
||||
|
||||
/* Declarations for plat_psci_handlers.c */
|
||||
int32_t tegra_soc_validate_power_state(unsigned int power_state,
|
||||
psci_power_state_t *req_state);
|
||||
|
|
@ -58,13 +81,21 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
|
|||
/* Declarations for plat_setup.c */
|
||||
const mmap_region_t *plat_get_mmio_map(void);
|
||||
uint32_t plat_get_console_from_id(int id);
|
||||
void plat_gic_setup(void);
|
||||
bl31_params_t *plat_get_bl31_params(void);
|
||||
plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
|
||||
|
||||
/* Declarations for plat_secondary.c */
|
||||
void plat_secondary_setup(void);
|
||||
int plat_lock_cpu_vectors(void);
|
||||
|
||||
/* Declarations for tegra_fiq_glue.c */
|
||||
void tegra_fiq_handler_setup(void);
|
||||
int tegra_fiq_get_intr_context(void);
|
||||
void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint);
|
||||
|
||||
/* Declarations for tegra_gic.c */
|
||||
void tegra_gic_setup(void);
|
||||
void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, unsigned int num_irqs);
|
||||
void tegra_gic_cpuif_deactivate(void);
|
||||
|
||||
/* Declarations for tegra_security.c */
|
||||
|
|
@ -83,6 +114,7 @@ int tegra_prepare_cpu_on_finish(unsigned long mpidr);
|
|||
/* Declarations for tegra_bl31_setup.c */
|
||||
plat_params_from_bl2_t *bl31_get_plat_params(void);
|
||||
int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes);
|
||||
void plat_early_platform_setup(void);
|
||||
|
||||
/* Declarations for tegra_delay_timer.c */
|
||||
void tegra_delay_timer_init(void);
|
||||
|
|
|
|||
|
|
@ -36,6 +36,14 @@ PSCI_EXTENDED_STATE_ID := 1
|
|||
# Disable the PSCI platform compatibility layer
|
||||
ENABLE_PLAT_COMPAT := 0
|
||||
|
||||
# Disable cache non-temporal hint for A57
|
||||
A57_DISABLE_NON_TEMPORAL_HINT := 0
|
||||
$(eval $(call add_define,A57_DISABLE_NON_TEMPORAL_HINT))
|
||||
|
||||
# Disable cache non-temporal hint for A53
|
||||
A53_DISABLE_NON_TEMPORAL_HINT := 0
|
||||
$(eval $(call add_define,A53_DISABLE_NON_TEMPORAL_HINT))
|
||||
|
||||
include plat/nvidia/tegra/common/tegra_common.mk
|
||||
include ${SOC_DIR}/platform_${TARGET_SOC}.mk
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -28,8 +28,11 @@
|
|||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <xlat_tables.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <bl_common.h>
|
||||
#include <tegra_def.h>
|
||||
#include <tegra_private.h>
|
||||
#include <xlat_tables.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* The Tegra power domain tree has a single system level power domain i.e. a
|
||||
|
|
@ -106,3 +109,11 @@ uint32_t plat_get_console_from_id(int id)
|
|||
|
||||
return tegra132_uart_addresses[id];
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Initialize the GIC and SGIs
|
||||
******************************************************************************/
|
||||
void plat_gic_setup(void)
|
||||
{
|
||||
tegra_gic_setup(NULL, 0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -28,8 +28,11 @@
|
|||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <bl_common.h>
|
||||
#include <console.h>
|
||||
#include <tegra_def.h>
|
||||
#include <tegra_private.h>
|
||||
#include <xlat_tables.h>
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -112,3 +115,11 @@ uint32_t plat_get_console_from_id(int id)
|
|||
|
||||
return tegra210_uart_addresses[id];
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Initialize the GIC and SGIs
|
||||
******************************************************************************/
|
||||
void plat_gic_setup(void)
|
||||
{
|
||||
tegra_gic_setup(NULL, 0);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue