allwinner: Add Allwinner H6 SoC support
The H6 is Allwinner's most recent SoC. It shares most peripherals with the other ARMv8 Allwinner SoCs (A64/H5), but has a completely different memory map. Introduce a separate platform target, which includes a different header file to cater for the address differences. Also add the new build target to the documentation. The new ATF platform name is "sun50i_h6". Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Andre Przywara
parent
700b6da722
commit
bed42a5d28
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@ -22,12 +22,18 @@ bl31.bin can be either copied (or sym-linked) into U-Boot's root directory,
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or the environment variable BL31 must contain the binary's path.
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See the respective `U-Boot documentation`_ for more details.
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To build:
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To build for machines with an A64 or H5 SoC:
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::
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make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1 bl31
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To build for machines with an H6 SoC:
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::
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make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h6 DEBUG=1 bl31
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.. _U-Boot documentation: http://git.denx.de/?p=u-boot.git;f=board/sunxi/README.sunxi64;hb=HEAD
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Trusted OS dispatcher
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@ -74,6 +74,9 @@ void bl31_platform_setup(void)
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case 0x1718:
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soc_name = "H5";
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break;
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case 0x1728:
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soc_name = "H6";
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break;
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default:
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soc_name = "unknown";
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break;
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@ -0,0 +1,27 @@
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SUNXI_CPUCFG_H__
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#define __SUNXI_CPUCFG_H__
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#include <sunxi_mmap.h>
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/* c = cluster, n = core */
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#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0010 + (c) * 0x10)
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#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_CPUCFG_BASE + 0x0014 + (c) * 0x10)
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#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_CPUCFG_BASE + 0x0024)
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#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_CPUCFG_BASE + 0x00c0)
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#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 4)
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#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8)
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#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8)
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#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
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#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
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#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
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(c) * 0x10 + (n) * 4)
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#endif /* __SUNXI_CPUCFG_H__ */
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@ -0,0 +1,61 @@
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SUNXI_MMAP_H__
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#define __SUNXI_MMAP_H__
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/* Memory regions */
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#define SUNXI_ROM_BASE 0x00000000
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#define SUNXI_ROM_SIZE 0x00010000
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#define SUNXI_SRAM_BASE 0x00020000
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#define SUNXI_SRAM_SIZE 0x00098000
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#define SUNXI_SRAM_A1_BASE 0x00020000
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#define SUNXI_SRAM_A1_SIZE 0x00008000
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#define SUNXI_SRAM_A2_BASE 0x00104000
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#define SUNXI_SRAM_A2_SIZE 0x00014000
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#define SUNXI_SRAM_C_BASE 0x00028000
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#define SUNXI_SRAM_C_SIZE 0x0001e000
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#define SUNXI_DEV_BASE 0x01000000
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#define SUNXI_DEV_SIZE 0x09000000
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#define SUNXI_DRAM_BASE 0x40000000
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#define SUNXI_DRAM_SIZE 0xc0000000
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/* Memory-mapped devices */
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#define SUNXI_SYSCON_BASE 0x03000000
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#define SUNXI_CPUCFG_BASE 0x09010000
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#define SUNXI_SID_BASE 0x03006000
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#define SUNXI_DMA_BASE 0x03002000
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#define SUNXI_MSGBOX_BASE 0x03003000
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#define SUNXI_CCU_BASE 0x03010000
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#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0xf00)
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#define SUNXI_PIO_BASE 0x030b0000
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#define SUNXI_TIMER_BASE 0x03009000
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#define SUNXI_WDOG_BASE 0x030090a0
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#define SUNXI_THS_BASE 0x05070400
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#define SUNXI_UART0_BASE 0x05000000
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#define SUNXI_UART1_BASE 0x05000400
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#define SUNXI_UART2_BASE 0x05000800
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#define SUNXI_UART3_BASE 0x05000c00
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#define SUNXI_I2C0_BASE 0x05002000
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#define SUNXI_I2C1_BASE 0x05002400
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#define SUNXI_I2C2_BASE 0x05002800
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#define SUNXI_I2C3_BASE 0x05002c00
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#define SUNXI_SPI0_BASE 0x05010000
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#define SUNXI_SPI1_BASE 0x05011000
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#define SUNXI_SCU_BASE 0x03020000
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#define SUNXI_GICD_BASE 0x03021000
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#define SUNXI_GICC_BASE 0x03022000
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#define SUNXI_R_TIMER_BASE 0x07020000
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#define SUNXI_R_INTC_BASE 0x07021000
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#define SUNXI_R_WDOG_BASE 0x07020400
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#define SUNXI_R_PRCM_BASE 0x07010000
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#define SUNXI_R_TWD_BASE 0x07020800
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#define SUNXI_R_CPUCFG_BASE 0x07000400
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#define SUNXI_R_I2C_BASE 0x07081400
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#define SUNXI_R_UART_BASE 0x07080000
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#define SUNXI_R_PIO_BASE 0x07022000
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#endif /* __SUNXI_MMAP_H__ */
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@ -0,0 +1,59 @@
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#
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# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include lib/xlat_tables_v2/xlat_tables.mk
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AW_PLAT := plat/allwinner
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PLAT_INCLUDES := -Iinclude/plat/arm/common \
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-Iinclude/plat/arm/common/aarch64 \
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-I${AW_PLAT}/common/include \
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-I${AW_PLAT}/${PLAT}/include
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PLAT_BL_COMMON_SOURCES := drivers/console/${ARCH}/console.S \
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drivers/ti/uart/${ARCH}/16550_console.S \
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${XLAT_TABLES_LIB_SRCS} \
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${AW_PLAT}/common/plat_helpers.S \
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${AW_PLAT}/common/sunxi_common.c
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BL31_SOURCES += drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v2/gicv2_helpers.c \
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drivers/arm/gic/v2/gicv2_main.c \
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drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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lib/cpus/${ARCH}/cortex_a53.S \
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plat/common/plat_gicv2.c \
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plat/common/plat_psci_common.c \
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${AW_PLAT}/common/sunxi_bl31_setup.c \
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${AW_PLAT}/common/sunxi_cpu_ops.c \
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${AW_PLAT}/common/sunxi_pm.c \
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${AW_PLAT}/common/sunxi_security.c \
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${AW_PLAT}/common/sunxi_topology.c
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# The bootloader is guaranteed to only run on CPU 0 by the boot ROM.
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COLD_BOOT_SINGLE_CPU := 1
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# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4.
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ERRATA_A53_835769 := 1
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ERRATA_A53_843419 := 1
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ERRATA_A53_855873 := 1
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# Disable the PSCI platform compatibility layer.
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ENABLE_PLAT_COMPAT := 0
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MULTI_CONSOLE_API := 1
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# Prohibit using deprecated interfaces. We rely on this for this platform.
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ERROR_DEPRECATED := 1
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# The reset vector can be changed for each CPU.
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PROGRAMMABLE_RESET_ADDRESS := 1
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# Allow mapping read-only data as execute-never.
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SEPARATE_CODE_AND_RODATA := 1
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# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL
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RESET_TO_BL31 := 1
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