Merge pull request #1250 from jollysxilinx/zynqmp-new-eemi-api
plat/xilinx: Add support for new platform management APIs for ZynqMP
This commit is contained in:
Dimitris Papastamos
GitHub
commit
bedf6f0b14
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@ -34,9 +34,14 @@
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* little space for growth.
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*/
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#ifndef ZYNQMP_ATF_MEM_BASE
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#if !DEBUG
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# define BL31_BASE 0xfffea000
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# define BL31_LIMIT 0xffffffff
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#else
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# define BL31_BASE 0x1000
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# define BL31_LIMIT 0x7ffff
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#endif
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#else
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# define BL31_BASE (ZYNQMP_ATF_MEM_BASE)
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# define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1)
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# ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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@ -77,6 +77,9 @@ BL31_SOURCES += drivers/arm/cci/cci.c \
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plat/xilinx/zynqmp/zynqmp_ipi.c \
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plat/xilinx/zynqmp/pm_service/pm_svc_main.c \
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plat/xilinx/zynqmp/pm_service/pm_api_sys.c \
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plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c \
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plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c \
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plat/xilinx/zynqmp/pm_service/pm_api_clock.c \
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plat/xilinx/zynqmp/pm_service/pm_ipi.c \
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plat/xilinx/zynqmp/pm_service/pm_client.c \
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plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.c
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,315 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* ZynqMP system level PM-API functions for clock control.
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*/
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#ifndef _PM_API_CLOCK_H_
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#define _PM_API_CLOCK_H_
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#include <utils_def.h>
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#include "pm_common.h"
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#define CLK_NAME_LEN U(15)
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#define MAX_PARENTS U(100)
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#define CLK_NA_PARENT -1
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#define CLK_DUMMY_PARENT -2
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/* Flags for parent id */
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#define PARENT_CLK_SELF U(0)
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#define PARENT_CLK_NODE1 U(1)
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#define PARENT_CLK_NODE2 U(2)
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#define PARENT_CLK_NODE3 U(3)
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#define PARENT_CLK_NODE4 U(4)
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#define PARENT_CLK_EXTERNAL U(5)
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#define PARENT_CLK_MIO0_MIO77 U(6)
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#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
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#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
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#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
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#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
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/* unused */
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#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
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#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
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#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
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#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
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#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
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#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
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#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
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/* parents need enable during gate/ungate, set rate and re-parent */
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#define CLK_OPS_PARENT_ENABLE BIT(12)
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#define CLK_FRAC BIT(13)
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#define CLK_DIVIDER_ONE_BASED BIT(0)
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#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
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#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
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#define CLK_DIVIDER_HIWORD_MASK BIT(3)
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#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
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#define CLK_DIVIDER_READ_ONLY BIT(5)
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#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
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#define END_OF_CLK "END_OF_CLK"
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//CLock Ids
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enum {
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CLK_IOPLL,
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CLK_RPLL,
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CLK_APLL,
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CLK_DPLL,
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CLK_VPLL,
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CLK_IOPLL_TO_FPD,
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CLK_RPLL_TO_FPD,
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CLK_APLL_TO_LPD,
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CLK_DPLL_TO_LPD,
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CLK_VPLL_TO_LPD,
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CLK_ACPU,
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CLK_ACPU_HALF,
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CLK_DBG_FPD,
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CLK_DBG_LPD,
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CLK_DBG_TRACE,
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CLK_DBG_TSTMP,
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CLK_DP_VIDEO_REF,
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CLK_DP_AUDIO_REF,
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CLK_DP_STC_REF,
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CLK_GDMA_REF,
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CLK_DPDMA_REF,
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CLK_DDR_REF,
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CLK_SATA_REF,
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CLK_PCIE_REF,
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CLK_GPU_REF,
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CLK_GPU_PP0_REF,
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CLK_GPU_PP1_REF,
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CLK_TOPSW_MAIN,
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CLK_TOPSW_LSBUS,
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CLK_GTGREF0_REF,
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CLK_LPD_SWITCH,
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CLK_LPD_LSBUS,
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CLK_USB0_BUS_REF,
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CLK_USB1_BUS_REF,
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CLK_USB3_DUAL_REF,
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CLK_USB0,
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CLK_USB1,
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CLK_CPU_R5,
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CLK_CPU_R5_CORE,
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CLK_CSU_SPB,
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CLK_CSU_PLL,
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CLK_PCAP,
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CLK_IOU_SWITCH,
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CLK_GEM_TSU_REF,
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CLK_GEM_TSU,
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CLK_GEM0_REF,
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CLK_GEM1_REF,
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CLK_GEM2_REF,
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CLK_GEM3_REF,
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CLK_GEM0_TX,
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CLK_GEM1_TX,
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CLK_GEM2_TX,
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CLK_GEM3_TX,
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CLK_QSPI_REF,
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CLK_SDIO0_REF,
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CLK_SDIO1_REF,
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CLK_UART0_REF,
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CLK_UART1_REF,
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CLK_SPI0_REF,
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CLK_SPI1_REF,
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CLK_NAND_REF,
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CLK_I2C0_REF,
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CLK_I2C1_REF,
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CLK_CAN0_REF,
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CLK_CAN1_REF,
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CLK_CAN0,
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CLK_CAN1,
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CLK_DLL_REF,
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CLK_ADMA_REF,
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CLK_TIMESTAMP_REF,
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CLK_AMS_REF,
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CLK_PL0_REF,
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CLK_PL1_REF,
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CLK_PL2_REF,
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CLK_PL3_REF,
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CLK_WDT,
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CLK_IOPLL_INT,
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CLK_IOPLL_PRE_SRC,
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CLK_IOPLL_HALF,
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CLK_IOPLL_INT_MUX,
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CLK_IOPLL_POST_SRC,
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CLK_RPLL_INT,
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CLK_RPLL_PRE_SRC,
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CLK_RPLL_HALF,
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CLK_RPLL_INT_MUX,
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CLK_RPLL_POST_SRC,
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CLK_APLL_INT,
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CLK_APLL_PRE_SRC,
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CLK_APLL_HALF,
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CLK_APLL_INT_MUX,
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CLK_APLL_POST_SRC,
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CLK_DPLL_INT,
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CLK_DPLL_PRE_SRC,
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CLK_DPLL_HALF,
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CLK_DPLL_INT_MUX,
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CLK_DPLL_POST_SRC,
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CLK_VPLL_INT,
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CLK_VPLL_PRE_SRC,
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CLK_VPLL_HALF,
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CLK_VPLL_INT_MUX,
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CLK_VPLL_POST_SRC,
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CLK_CAN0_MIO,
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CLK_CAN1_MIO,
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END_OF_OUTPUT_CLKS,
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};
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#define CLK_MAX_OUTPUT_CLK (unsigned int)(END_OF_OUTPUT_CLKS)
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//External clock ids
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enum {
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EXT_CLK_PSS_REF = END_OF_OUTPUT_CLKS,
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EXT_CLK_VIDEO,
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EXT_CLK_PSS_ALT_REF,
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EXT_CLK_AUX_REF,
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EXT_CLK_GT_CRX_REF,
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EXT_CLK_SWDT0,
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EXT_CLK_SWDT1,
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EXT_CLK_GEM0_EMIO,
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EXT_CLK_GEM1_EMIO,
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EXT_CLK_GEM2_EMIO,
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EXT_CLK_GEM3_EMIO,
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EXT_CLK_MIO50_OR_MIO51,
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EXT_CLK_MIO0,
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EXT_CLK_MIO1,
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EXT_CLK_MIO2,
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EXT_CLK_MIO3,
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EXT_CLK_MIO4,
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EXT_CLK_MIO5,
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EXT_CLK_MIO6,
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EXT_CLK_MIO7,
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EXT_CLK_MIO8,
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EXT_CLK_MIO9,
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EXT_CLK_MIO10,
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EXT_CLK_MIO11,
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EXT_CLK_MIO12,
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EXT_CLK_MIO13,
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EXT_CLK_MIO14,
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EXT_CLK_MIO15,
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EXT_CLK_MIO16,
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EXT_CLK_MIO17,
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EXT_CLK_MIO18,
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EXT_CLK_MIO19,
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EXT_CLK_MIO20,
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EXT_CLK_MIO21,
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EXT_CLK_MIO22,
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EXT_CLK_MIO23,
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EXT_CLK_MIO24,
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EXT_CLK_MIO25,
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EXT_CLK_MIO26,
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EXT_CLK_MIO27,
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EXT_CLK_MIO28,
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EXT_CLK_MIO29,
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EXT_CLK_MIO30,
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EXT_CLK_MIO31,
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EXT_CLK_MIO32,
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EXT_CLK_MIO33,
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EXT_CLK_MIO34,
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EXT_CLK_MIO35,
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EXT_CLK_MIO36,
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EXT_CLK_MIO37,
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EXT_CLK_MIO38,
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EXT_CLK_MIO39,
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EXT_CLK_MIO40,
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EXT_CLK_MIO41,
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EXT_CLK_MIO42,
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EXT_CLK_MIO43,
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EXT_CLK_MIO44,
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EXT_CLK_MIO45,
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EXT_CLK_MIO46,
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EXT_CLK_MIO47,
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EXT_CLK_MIO48,
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EXT_CLK_MIO49,
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EXT_CLK_MIO50,
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EXT_CLK_MIO51,
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EXT_CLK_MIO52,
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EXT_CLK_MIO53,
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EXT_CLK_MIO54,
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EXT_CLK_MIO55,
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EXT_CLK_MIO56,
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EXT_CLK_MIO57,
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EXT_CLK_MIO58,
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EXT_CLK_MIO59,
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EXT_CLK_MIO60,
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EXT_CLK_MIO61,
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EXT_CLK_MIO62,
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EXT_CLK_MIO63,
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EXT_CLK_MIO64,
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EXT_CLK_MIO65,
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EXT_CLK_MIO66,
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EXT_CLK_MIO67,
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EXT_CLK_MIO68,
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EXT_CLK_MIO69,
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EXT_CLK_MIO70,
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EXT_CLK_MIO71,
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EXT_CLK_MIO72,
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EXT_CLK_MIO73,
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EXT_CLK_MIO74,
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EXT_CLK_MIO75,
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EXT_CLK_MIO76,
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EXT_CLK_MIO77,
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END_OF_CLKS,
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};
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#define CLK_MAX (unsigned int)(END_OF_CLKS)
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//CLock types
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#define CLK_TYPE_OUTPUT 0U
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#define CLK_TYPE_EXTERNAL 1U
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//Topology types
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#define TYPE_INVALID 0U
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#define TYPE_MUX 1U
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#define TYPE_PLL 2U
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#define TYPE_FIXEDFACTOR 3U
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#define TYPE_DIV1 4U
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#define TYPE_DIV2 5U
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#define TYPE_GATE 6U
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enum pm_ret_status pm_api_clock_get_name(unsigned int clock_id, char *name);
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enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id,
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unsigned int index,
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uint32_t *topology);
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enum pm_ret_status pm_api_clock_get_fixedfactor_params(unsigned int clock_id,
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uint32_t *mul,
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uint32_t *div);
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enum pm_ret_status pm_api_clock_get_parents(unsigned int clock_id,
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unsigned int index,
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uint32_t *parents);
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enum pm_ret_status pm_api_clock_get_attributes(unsigned int clock_id,
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uint32_t *attr);
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enum pm_ret_status pm_api_clock_enable(unsigned int clock_id);
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enum pm_ret_status pm_api_clock_disable(unsigned int clock_id);
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enum pm_ret_status pm_api_clock_getstate(unsigned int clock_id,
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unsigned int *state);
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enum pm_ret_status pm_api_clock_setdivider(unsigned int clock_id,
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unsigned int divider);
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enum pm_ret_status pm_api_clock_getdivider(unsigned int clock_id,
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unsigned int *divider);
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enum pm_ret_status pm_api_clock_setrate(unsigned int clock_id,
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uint64_t rate);
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enum pm_ret_status pm_api_clock_getrate(unsigned int clock_id,
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uint64_t *rate);
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enum pm_ret_status pm_api_clock_setparent(unsigned int clock_id,
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unsigned int parent_idx);
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enum pm_ret_status pm_api_clock_getparent(unsigned int clock_id,
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unsigned int *parent_idx);
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enum pm_ret_status pm_api_clk_set_pll_mode(unsigned int pll,
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unsigned int mode);
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enum pm_ret_status pm_api_clk_get_pll_mode(unsigned int pll,
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unsigned int *mode);
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enum pm_ret_status pm_api_clk_set_pll_frac_data(unsigned int pll,
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unsigned int data);
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enum pm_ret_status pm_api_clk_get_pll_frac_data(unsigned int pll,
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unsigned int *data);
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#endif /* _PM_API_CLOCK_H_ */
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@ -0,0 +1,549 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* ZynqMP system level PM-API functions for ioctl.
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*/
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#include <arch_helpers.h>
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#include <delay_timer.h>
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#include <mmio.h>
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#include <platform.h>
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#include "pm_api_clock.h"
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#include "pm_api_ioctl.h"
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#include "pm_api_sys.h"
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#include "pm_client.h"
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#include "pm_common.h"
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#include "pm_ipi.h"
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#include "../zynqmp_def.h"
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/**
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* pm_ioctl_get_rpu_oper_mode () - Get current RPU operation mode
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* @mode Buffer to store value of oper mode(Split/Lock-step)
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*
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* This function provides current configured RPU operational mode.
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*
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* @return Returns status, either success or error+reason
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*/
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static enum pm_ret_status pm_ioctl_get_rpu_oper_mode(unsigned int *mode)
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{
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unsigned int val;
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val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL);
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val &= ZYNQMP_SLSPLIT_MASK;
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if (val == 0)
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*mode = PM_RPU_MODE_LOCKSTEP;
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else
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*mode = PM_RPU_MODE_SPLIT;
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return PM_RET_SUCCESS;
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}
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/**
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* pm_ioctl_set_rpu_oper_mode () - Configure RPU operation mode
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* @mode Value to set for oper mode(Split/Lock-step)
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*
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* This function configures RPU operational mode(Split/Lock-step).
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* It also sets TCM combined mode in RPU lock-step and TCM non-combined
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* mode for RPU split mode. In case of Lock step mode, RPU1's output is
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* clamped.
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*
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* @return Returns status, either success or error+reason
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*/
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static enum pm_ret_status pm_ioctl_set_rpu_oper_mode(unsigned int mode)
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{
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unsigned int val;
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if (mmio_read_32(CRL_APB_RST_LPD_TOP) && CRL_APB_RPU_AMBA_RESET)
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return PM_RET_ERROR_ACCESS;
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val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL);
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if (mode == PM_RPU_MODE_SPLIT) {
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val |= ZYNQMP_SLSPLIT_MASK;
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val &= ~ZYNQMP_TCM_COMB_MASK;
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val &= ~ZYNQMP_SLCLAMP_MASK;
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} else if (mode == PM_RPU_MODE_LOCKSTEP) {
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val &= ~ZYNQMP_SLSPLIT_MASK;
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val |= ZYNQMP_TCM_COMB_MASK;
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val |= ZYNQMP_SLCLAMP_MASK;
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} else {
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return PM_RET_ERROR_ARGS;
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}
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mmio_write_32(ZYNQMP_RPU_GLBL_CNTL, val);
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return PM_RET_SUCCESS;
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}
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/**
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* pm_ioctl_config_boot_addr() - Configure RPU boot address
|
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* @nid Node ID of RPU
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* @value Value to set for boot address (TCM/OCM)
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*
|
||||
* This function configures RPU boot address(memory).
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_ioctl_config_boot_addr(enum pm_node_id nid,
|
||||
unsigned int value)
|
||||
{
|
||||
unsigned int rpu_cfg_addr, val;
|
||||
|
||||
if (nid == NODE_RPU_0)
|
||||
rpu_cfg_addr = ZYNQMP_RPU0_CFG;
|
||||
else if (nid == NODE_RPU_1)
|
||||
rpu_cfg_addr = ZYNQMP_RPU1_CFG;
|
||||
else
|
||||
return PM_RET_ERROR_ARGS;
|
||||
|
||||
val = mmio_read_32(rpu_cfg_addr);
|
||||
|
||||
if (value == PM_RPU_BOOTMEM_LOVEC)
|
||||
val &= ~ZYNQMP_VINITHI_MASK;
|
||||
else if (value == PM_RPU_BOOTMEM_HIVEC)
|
||||
val |= ZYNQMP_VINITHI_MASK;
|
||||
else
|
||||
return PM_RET_ERROR_ARGS;
|
||||
|
||||
mmio_write_32(rpu_cfg_addr, val);
|
||||
|
||||
return PM_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_ioctl_config_tcm_comb() - Configure TCM combined mode
|
||||
* @value Value to set (Split/Combined)
|
||||
*
|
||||
* This function configures TCM to be in split mode or combined
|
||||
* mode.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_ioctl_config_tcm_comb(unsigned int value)
|
||||
{
|
||||
unsigned int val;
|
||||
|
||||
val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL);
|
||||
|
||||
if (value == PM_RPU_TCM_SPLIT)
|
||||
val &= ~ZYNQMP_TCM_COMB_MASK;
|
||||
else if (value == PM_RPU_TCM_COMB)
|
||||
val |= ZYNQMP_TCM_COMB_MASK;
|
||||
else
|
||||
return PM_RET_ERROR_ARGS;
|
||||
|
||||
mmio_write_32(ZYNQMP_RPU_GLBL_CNTL, val);
|
||||
|
||||
return PM_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_ioctl_set_tapdelay_bypass() - Enable/Disable tap delay bypass
|
||||
* @type Type of tap delay to enable/disable (e.g. QSPI)
|
||||
* @value Enable/Disable
|
||||
*
|
||||
* This function enable/disable tap delay bypass.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_ioctl_set_tapdelay_bypass(unsigned int type,
|
||||
unsigned int value)
|
||||
{
|
||||
if ((value != PM_TAPDELAY_BYPASS_ENABLE &&
|
||||
value != PM_TAPDELAY_BYPASS_DISABLE) || type >= PM_TAPDELAY_MAX)
|
||||
return PM_RET_ERROR_ARGS;
|
||||
|
||||
return pm_mmio_write(IOU_TAPDLY_BYPASS, TAP_DELAY_MASK, value << type);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_ioctl_set_sgmii_mode() - Set SGMII mode for the GEM device
|
||||
* @nid Node ID of the device
|
||||
* @value Enable/Disable
|
||||
*
|
||||
* This function enable/disable SGMII mode for the GEM device.
|
||||
* While enabling SGMII mode, it also ties the GEM PCS Signal
|
||||
* Detect to 1 and selects EMIO for RX clock generation.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_ioctl_set_sgmii_mode(enum pm_node_id nid,
|
||||
unsigned int value)
|
||||
{
|
||||
unsigned int val, mask, shift;
|
||||
enum pm_ret_status ret;
|
||||
|
||||
if (value != PM_SGMII_DISABLE && value != PM_SGMII_ENABLE)
|
||||
return PM_RET_ERROR_ARGS;
|
||||
|
||||
switch (nid) {
|
||||
case NODE_ETH_0:
|
||||
shift = 0;
|
||||
break;
|
||||
case NODE_ETH_1:
|
||||
shift = 1;
|
||||
break;
|
||||
case NODE_ETH_2:
|
||||
shift = 2;
|
||||
break;
|
||||
case NODE_ETH_3:
|
||||
shift = 3;
|
||||
break;
|
||||
default:
|
||||
return PM_RET_ERROR_ARGS;
|
||||
}
|
||||
|
||||
if (value == PM_SGMII_DISABLE) {
|
||||
mask = GEM_SGMII_MASK << GEM_CLK_CTRL_OFFSET * shift;
|
||||
ret = pm_mmio_write(IOU_GEM_CLK_CTRL, mask, 0U);
|
||||
} else {
|
||||
/* Tie the GEM PCS Signal Detect to 1 */
|
||||
mask = SGMII_SD_MASK << SGMII_SD_OFFSET * shift;
|
||||
val = SGMII_PCS_SD_1 << SGMII_SD_OFFSET * shift;
|
||||
ret = pm_mmio_write(IOU_GEM_CTRL, mask, val);
|
||||
if (ret != PM_RET_SUCCESS)
|
||||
return ret;
|
||||
|
||||
/* Set the GEM to SGMII mode */
|
||||
mask = GEM_CLK_CTRL_MASK << GEM_CLK_CTRL_OFFSET * shift;
|
||||
val = GEM_RX_SRC_SEL_GTR | GEM_SGMII_MODE;
|
||||
val <<= GEM_CLK_CTRL_OFFSET * shift;
|
||||
ret = pm_mmio_write(IOU_GEM_CLK_CTRL, mask, val);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_ioctl_sd_dll_reset() - Reset DLL logic
|
||||
* @nid Node ID of the device
|
||||
* @type Reset type
|
||||
*
|
||||
* This function resets DLL logic for the SD device.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_ioctl_sd_dll_reset(enum pm_node_id nid,
|
||||
unsigned int type)
|
||||
{
|
||||
unsigned int mask, val;
|
||||
enum pm_ret_status ret;
|
||||
|
||||
if (nid == NODE_SD_0) {
|
||||
mask = ZYNQMP_SD0_DLL_RST_MASK;
|
||||
val = ZYNQMP_SD0_DLL_RST;
|
||||
} else if (nid == NODE_SD_1) {
|
||||
mask = ZYNQMP_SD1_DLL_RST_MASK;
|
||||
val = ZYNQMP_SD1_DLL_RST;
|
||||
} else {
|
||||
return PM_RET_ERROR_ARGS;
|
||||
}
|
||||
|
||||
switch (type) {
|
||||
case PM_DLL_RESET_ASSERT:
|
||||
case PM_DLL_RESET_PULSE:
|
||||
ret = pm_mmio_write(ZYNQMP_SD_DLL_CTRL, mask, val);
|
||||
if (ret != PM_RET_SUCCESS)
|
||||
return ret;
|
||||
|
||||
if (type == PM_DLL_RESET_ASSERT)
|
||||
break;
|
||||
mdelay(1);
|
||||
case PM_DLL_RESET_RELEASE:
|
||||
ret = pm_mmio_write(ZYNQMP_SD_DLL_CTRL, mask, 0);
|
||||
break;
|
||||
default:
|
||||
ret = PM_RET_ERROR_ARGS;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_ioctl_sd_set_tapdelay() - Set tap delay for the SD device
|
||||
* @nid Node ID of the device
|
||||
* @type Type of tap delay to set (input/output)
|
||||
* @value Value to set fot the tap delay
|
||||
*
|
||||
* This function sets input/output tap delay for the SD device.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_ioctl_sd_set_tapdelay(enum pm_node_id nid,
|
||||
enum tap_delay_type type,
|
||||
unsigned int value)
|
||||
{
|
||||
unsigned int shift;
|
||||
enum pm_ret_status ret;
|
||||
|
||||
if (nid == NODE_SD_0)
|
||||
shift = 0;
|
||||
else if (nid == NODE_SD_1)
|
||||
shift = ZYNQMP_SD_TAP_OFFSET;
|
||||
else
|
||||
return PM_RET_ERROR_ARGS;
|
||||
|
||||
ret = pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_ASSERT);
|
||||
if (ret != PM_RET_SUCCESS)
|
||||
return ret;
|
||||
|
||||
if (type == PM_TAPDELAY_INPUT) {
|
||||
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
|
||||
(ZYNQMP_SD_ITAPCHGWIN_MASK << shift),
|
||||
(ZYNQMP_SD_ITAPCHGWIN << shift));
|
||||
if (ret != PM_RET_SUCCESS)
|
||||
goto reset_release;
|
||||
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
|
||||
(ZYNQMP_SD_ITAPDLYENA_MASK << shift),
|
||||
(ZYNQMP_SD_ITAPDLYENA << shift));
|
||||
if (ret != PM_RET_SUCCESS)
|
||||
goto reset_release;
|
||||
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
|
||||
(ZYNQMP_SD_ITAPDLYSEL_MASK << shift),
|
||||
(value << shift));
|
||||
if (ret != PM_RET_SUCCESS)
|
||||
goto reset_release;
|
||||
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
|
||||
(ZYNQMP_SD_ITAPCHGWIN_MASK << shift), 0);
|
||||
} else if (type == PM_TAPDELAY_OUTPUT) {
|
||||
ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
|
||||
(ZYNQMP_SD_OTAPDLYENA_MASK << shift),
|
||||
(ZYNQMP_SD_OTAPDLYENA << shift));
|
||||
if (ret != PM_RET_SUCCESS)
|
||||
goto reset_release;
|
||||
ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
|
||||
(ZYNQMP_SD_OTAPDLYSEL_MASK << shift),
|
||||
(value << shift));
|
||||
} else {
|
||||
ret = PM_RET_ERROR_ARGS;
|
||||
}
|
||||
|
||||
reset_release:
|
||||
pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_RELEASE);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_ioctl_set_pll_frac_mode() - Ioctl function for
|
||||
* setting pll mode
|
||||
* @pll PLL id
|
||||
* @mode Mode fraction/integar
|
||||
*
|
||||
* This function sets PLL mode
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_ioctl_set_pll_frac_mode
|
||||
(unsigned int pll, unsigned int mode)
|
||||
{
|
||||
return pm_api_clk_set_pll_mode(pll, mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_ioctl_get_pll_frac_mode() - Ioctl function for
|
||||
* getting pll mode
|
||||
* @pll PLL id
|
||||
* @mode Mode fraction/integar
|
||||
*
|
||||
* This function return current PLL mode
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_ioctl_get_pll_frac_mode
|
||||
(unsigned int pll, unsigned int *mode)
|
||||
{
|
||||
return pm_api_clk_get_pll_mode(pll, mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_ioctl_set_pll_frac_data() - Ioctl function for
|
||||
* setting pll fraction data
|
||||
* @pll PLL id
|
||||
* @data fraction data
|
||||
*
|
||||
* This function sets fraction data.
|
||||
* It is valid for fraction mode only.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_ioctl_set_pll_frac_data
|
||||
(unsigned int pll, unsigned int data)
|
||||
{
|
||||
return pm_api_clk_set_pll_frac_data(pll, data);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_ioctl_get_pll_frac_data() - Ioctl function for
|
||||
* getting pll fraction data
|
||||
* @pll PLL id
|
||||
* @data fraction data
|
||||
*
|
||||
* This function returns fraction data value.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_ioctl_get_pll_frac_data
|
||||
(unsigned int pll, unsigned int *data)
|
||||
{
|
||||
return pm_api_clk_get_pll_frac_data(pll, data);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_ioctl_write_ggs() - Ioctl function for writing
|
||||
* global general storage (ggs)
|
||||
* @index GGS register index
|
||||
* @value Register value to be written
|
||||
*
|
||||
* This function writes value to GGS register.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_ioctl_write_ggs(unsigned int index,
|
||||
unsigned int value)
|
||||
{
|
||||
if (index >= GGS_NUM_REGS)
|
||||
return PM_RET_ERROR_ARGS;
|
||||
|
||||
return pm_mmio_write(GGS_BASEADDR + (index << 2),
|
||||
0xFFFFFFFFU, value);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_ioctl_read_ggs() - Ioctl function for reading
|
||||
* global general storage (ggs)
|
||||
* @index GGS register index
|
||||
* @value Register value
|
||||
*
|
||||
* This function returns GGS register value.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_ioctl_read_ggs(unsigned int index,
|
||||
unsigned int *value)
|
||||
{
|
||||
if (index >= GGS_NUM_REGS)
|
||||
return PM_RET_ERROR_ARGS;
|
||||
|
||||
return pm_mmio_read(GGS_BASEADDR + (index << 2), value);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_ioctl_write_pggs() - Ioctl function for writing persistent
|
||||
* global general storage (pggs)
|
||||
* @index PGGS register index
|
||||
* @value Register value to be written
|
||||
*
|
||||
* This function writes value to PGGS register.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_ioctl_write_pggs(unsigned int index,
|
||||
unsigned int value)
|
||||
{
|
||||
if (index >= PGGS_NUM_REGS)
|
||||
return PM_RET_ERROR_ARGS;
|
||||
|
||||
return pm_mmio_write(PGGS_BASEADDR + (index << 2),
|
||||
0xFFFFFFFFU, value);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_ioctl_read_pggs() - Ioctl function for reading persistent
|
||||
* global general storage (pggs)
|
||||
* @index PGGS register index
|
||||
* @value Register value
|
||||
*
|
||||
* This function returns PGGS register value.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_ioctl_read_pggs(unsigned int index,
|
||||
unsigned int *value)
|
||||
{
|
||||
if (index >= PGGS_NUM_REGS)
|
||||
return PM_RET_ERROR_ARGS;
|
||||
|
||||
return pm_mmio_read(PGGS_BASEADDR + (index << 2), value);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_api_ioctl() - PM IOCTL API for device control and configs
|
||||
* @node_id Node ID of the device
|
||||
* @ioctl_id ID of the requested IOCTL
|
||||
* @arg1 Argument 1 to requested IOCTL call
|
||||
* @arg2 Argument 2 to requested IOCTL call
|
||||
* @value Returned output value
|
||||
*
|
||||
* This function calls IOCTL to firmware for device control and configuration.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
enum pm_ret_status pm_api_ioctl(enum pm_node_id nid,
|
||||
unsigned int ioctl_id,
|
||||
unsigned int arg1,
|
||||
unsigned int arg2,
|
||||
unsigned int *value)
|
||||
{
|
||||
enum pm_ret_status ret;
|
||||
|
||||
switch (ioctl_id) {
|
||||
case IOCTL_GET_RPU_OPER_MODE:
|
||||
ret = pm_ioctl_get_rpu_oper_mode(value);
|
||||
break;
|
||||
case IOCTL_SET_RPU_OPER_MODE:
|
||||
ret = pm_ioctl_set_rpu_oper_mode(arg1);
|
||||
break;
|
||||
case IOCTL_RPU_BOOT_ADDR_CONFIG:
|
||||
ret = pm_ioctl_config_boot_addr(nid, arg1);
|
||||
break;
|
||||
case IOCTL_TCM_COMB_CONFIG:
|
||||
ret = pm_ioctl_config_tcm_comb(arg1);
|
||||
break;
|
||||
case IOCTL_SET_TAPDELAY_BYPASS:
|
||||
ret = pm_ioctl_set_tapdelay_bypass(arg1, arg2);
|
||||
break;
|
||||
case IOCTL_SET_SGMII_MODE:
|
||||
ret = pm_ioctl_set_sgmii_mode(nid, arg1);
|
||||
break;
|
||||
case IOCTL_SD_DLL_RESET:
|
||||
ret = pm_ioctl_sd_dll_reset(nid, arg1);
|
||||
break;
|
||||
case IOCTL_SET_SD_TAPDELAY:
|
||||
ret = pm_ioctl_sd_set_tapdelay(nid, arg1, arg2);
|
||||
break;
|
||||
case IOCTL_SET_PLL_FRAC_MODE:
|
||||
ret = pm_ioctl_set_pll_frac_mode(arg1, arg2);
|
||||
break;
|
||||
case IOCTL_GET_PLL_FRAC_MODE:
|
||||
ret = pm_ioctl_get_pll_frac_mode(arg1, value);
|
||||
break;
|
||||
case IOCTL_SET_PLL_FRAC_DATA:
|
||||
ret = pm_ioctl_set_pll_frac_data(arg1, arg2);
|
||||
break;
|
||||
case IOCTL_GET_PLL_FRAC_DATA:
|
||||
ret = pm_ioctl_get_pll_frac_data(arg1, value);
|
||||
break;
|
||||
case IOCTL_WRITE_GGS:
|
||||
ret = pm_ioctl_write_ggs(arg1, arg2);
|
||||
break;
|
||||
case IOCTL_READ_GGS:
|
||||
ret = pm_ioctl_read_ggs(arg1, value);
|
||||
break;
|
||||
case IOCTL_WRITE_PGGS:
|
||||
ret = pm_ioctl_write_pggs(arg1, arg2);
|
||||
break;
|
||||
case IOCTL_READ_PGGS:
|
||||
ret = pm_ioctl_read_pggs(arg1, value);
|
||||
break;
|
||||
default:
|
||||
ret = PM_RET_ERROR_NOTSUPPORTED;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* ZynqMP system level PM-API functions for pin control.
|
||||
*/
|
||||
|
||||
#ifndef _PM_API_IOCTL_H_
|
||||
#define _PM_API_IOCTL_H_
|
||||
|
||||
#include "pm_common.h"
|
||||
|
||||
//ioctl id
|
||||
enum {
|
||||
IOCTL_GET_RPU_OPER_MODE,
|
||||
IOCTL_SET_RPU_OPER_MODE,
|
||||
IOCTL_RPU_BOOT_ADDR_CONFIG,
|
||||
IOCTL_TCM_COMB_CONFIG,
|
||||
IOCTL_SET_TAPDELAY_BYPASS,
|
||||
IOCTL_SET_SGMII_MODE,
|
||||
IOCTL_SD_DLL_RESET,
|
||||
IOCTL_SET_SD_TAPDELAY,
|
||||
/* Ioctl for clock driver */
|
||||
IOCTL_SET_PLL_FRAC_MODE,
|
||||
IOCTL_GET_PLL_FRAC_MODE,
|
||||
IOCTL_SET_PLL_FRAC_DATA,
|
||||
IOCTL_GET_PLL_FRAC_DATA,
|
||||
IOCTL_WRITE_GGS,
|
||||
IOCTL_READ_GGS,
|
||||
IOCTL_WRITE_PGGS,
|
||||
IOCTL_READ_PGGS,
|
||||
};
|
||||
|
||||
//RPU operation mode
|
||||
#define PM_RPU_MODE_LOCKSTEP 0U
|
||||
#define PM_RPU_MODE_SPLIT 1U
|
||||
|
||||
//RPU boot mem
|
||||
#define PM_RPU_BOOTMEM_LOVEC 0U
|
||||
#define PM_RPU_BOOTMEM_HIVEC 1U
|
||||
|
||||
//RPU tcm mpde
|
||||
#define PM_RPU_TCM_SPLIT 0U
|
||||
#define PM_RPU_TCM_COMB 1U
|
||||
|
||||
//tap delay signal type
|
||||
#define PM_TAPDELAY_NAND_DQS_IN 0U
|
||||
#define PM_TAPDELAY_NAND_DQS_OUT 1U
|
||||
#define PM_TAPDELAY_QSPI 2U
|
||||
#define PM_TAPDELAY_MAX 3U
|
||||
|
||||
//tap delay bypass
|
||||
#define PM_TAPDELAY_BYPASS_DISABLE 0U
|
||||
#define PM_TAPDELAY_BYPASS_ENABLE 1U
|
||||
|
||||
//sgmii mode
|
||||
#define PM_SGMII_DISABLE 0U
|
||||
#define PM_SGMII_ENABLE 1U
|
||||
|
||||
enum tap_delay_type {
|
||||
PM_TAPDELAY_INPUT,
|
||||
PM_TAPDELAY_OUTPUT,
|
||||
};
|
||||
|
||||
//dll reset type
|
||||
#define PM_DLL_RESET_ASSERT 0U
|
||||
#define PM_DLL_RESET_RELEASE 1U
|
||||
#define PM_DLL_RESET_PULSE 2U
|
||||
|
||||
enum pm_ret_status pm_api_ioctl(enum pm_node_id nid,
|
||||
unsigned int ioctl_id,
|
||||
unsigned int arg1,
|
||||
unsigned int arg2,
|
||||
unsigned int *value);
|
||||
#endif /* _PM_API_IOCTL_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,734 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* ZynqMP system level PM-API functions for pin control.
|
||||
*/
|
||||
|
||||
#ifndef _PM_API_PINCTRL_H_
|
||||
#define _PM_API_PINCTRL_H_
|
||||
|
||||
#include "pm_common.h"
|
||||
|
||||
#define FUNCTION_NAME_LEN U(16)
|
||||
#define GROUPS_PAYLOAD_LEN U(12)
|
||||
#define NUM_GROUPS_PER_RESP U(6)
|
||||
#define END_OF_FUNCTION "END_OF_FUNCTION"
|
||||
#define END_OF_GROUPS -1
|
||||
#define PINCTRL_GRP_RESERVED -2
|
||||
|
||||
//pinctrl function ids
|
||||
enum {
|
||||
PINCTRL_FUNC_CAN0,
|
||||
PINCTRL_FUNC_CAN1,
|
||||
PINCTRL_FUNC_ETHERNET0,
|
||||
PINCTRL_FUNC_ETHERNET1,
|
||||
PINCTRL_FUNC_ETHERNET2,
|
||||
PINCTRL_FUNC_ETHERNET3,
|
||||
PINCTRL_FUNC_GEMTSU0,
|
||||
PINCTRL_FUNC_GPIO0,
|
||||
PINCTRL_FUNC_I2C0,
|
||||
PINCTRL_FUNC_I2C1,
|
||||
PINCTRL_FUNC_MDIO0,
|
||||
PINCTRL_FUNC_MDIO1,
|
||||
PINCTRL_FUNC_MDIO2,
|
||||
PINCTRL_FUNC_MDIO3,
|
||||
PINCTRL_FUNC_QSPI0,
|
||||
PINCTRL_FUNC_QSPI_FBCLK,
|
||||
PINCTRL_FUNC_QSPI_SS,
|
||||
PINCTRL_FUNC_SPI0,
|
||||
PINCTRL_FUNC_SPI1,
|
||||
PINCTRL_FUNC_SPI0_SS,
|
||||
PINCTRL_FUNC_SPI1_SS,
|
||||
PINCTRL_FUNC_SDIO0,
|
||||
PINCTRL_FUNC_SDIO0_PC,
|
||||
PINCTRL_FUNC_SDIO0_CD,
|
||||
PINCTRL_FUNC_SDIO0_WP,
|
||||
PINCTRL_FUNC_SDIO1,
|
||||
PINCTRL_FUNC_SDIO1_PC,
|
||||
PINCTRL_FUNC_SDIO1_CD,
|
||||
PINCTRL_FUNC_SDIO1_WP,
|
||||
PINCTRL_FUNC_NAND0,
|
||||
PINCTRL_FUNC_NAND0_CE,
|
||||
PINCTRL_FUNC_NAND0_RB,
|
||||
PINCTRL_FUNC_NAND0_DQS,
|
||||
PINCTRL_FUNC_TTC0_CLK,
|
||||
PINCTRL_FUNC_TTC0_WAV,
|
||||
PINCTRL_FUNC_TTC1_CLK,
|
||||
PINCTRL_FUNC_TTC1_WAV,
|
||||
PINCTRL_FUNC_TTC2_CLK,
|
||||
PINCTRL_FUNC_TTC2_WAV,
|
||||
PINCTRL_FUNC_TTC3_CLK,
|
||||
PINCTRL_FUNC_TTC3_WAV,
|
||||
PINCTRL_FUNC_UART0,
|
||||
PINCTRL_FUNC_UART1,
|
||||
PINCTRL_FUNC_USB0,
|
||||
PINCTRL_FUNC_USB1,
|
||||
PINCTRL_FUNC_SWDT0_CLK,
|
||||
PINCTRL_FUNC_SWDT0_RST,
|
||||
PINCTRL_FUNC_SWDT1_CLK,
|
||||
PINCTRL_FUNC_SWDT1_RST,
|
||||
PINCTRL_FUNC_PMU0,
|
||||
PINCTRL_FUNC_PCIE0,
|
||||
PINCTRL_FUNC_CSU0,
|
||||
PINCTRL_FUNC_DPAUX0,
|
||||
PINCTRL_FUNC_PJTAG0,
|
||||
PINCTRL_FUNC_TRACE0,
|
||||
PINCTRL_FUNC_TRACE0_CLK,
|
||||
PINCTRL_FUNC_TESTSCAN0,
|
||||
END_FUNCTION,
|
||||
};
|
||||
|
||||
#define MAX_FUNCTION (unsigned int)(END_FUNCTION)
|
||||
|
||||
// pinctrl pin numbers
|
||||
enum {
|
||||
PINCTRL_PIN_0,
|
||||
PINCTRL_PIN_1,
|
||||
PINCTRL_PIN_2,
|
||||
PINCTRL_PIN_3,
|
||||
PINCTRL_PIN_4,
|
||||
PINCTRL_PIN_5,
|
||||
PINCTRL_PIN_6,
|
||||
PINCTRL_PIN_7,
|
||||
PINCTRL_PIN_8,
|
||||
PINCTRL_PIN_9,
|
||||
PINCTRL_PIN_10,
|
||||
PINCTRL_PIN_11,
|
||||
PINCTRL_PIN_12,
|
||||
PINCTRL_PIN_13,
|
||||
PINCTRL_PIN_14,
|
||||
PINCTRL_PIN_15,
|
||||
PINCTRL_PIN_16,
|
||||
PINCTRL_PIN_17,
|
||||
PINCTRL_PIN_18,
|
||||
PINCTRL_PIN_19,
|
||||
PINCTRL_PIN_20,
|
||||
PINCTRL_PIN_21,
|
||||
PINCTRL_PIN_22,
|
||||
PINCTRL_PIN_23,
|
||||
PINCTRL_PIN_24,
|
||||
PINCTRL_PIN_25,
|
||||
PINCTRL_PIN_26,
|
||||
PINCTRL_PIN_27,
|
||||
PINCTRL_PIN_28,
|
||||
PINCTRL_PIN_29,
|
||||
PINCTRL_PIN_30,
|
||||
PINCTRL_PIN_31,
|
||||
PINCTRL_PIN_32,
|
||||
PINCTRL_PIN_33,
|
||||
PINCTRL_PIN_34,
|
||||
PINCTRL_PIN_35,
|
||||
PINCTRL_PIN_36,
|
||||
PINCTRL_PIN_37,
|
||||
PINCTRL_PIN_38,
|
||||
PINCTRL_PIN_39,
|
||||
PINCTRL_PIN_40,
|
||||
PINCTRL_PIN_41,
|
||||
PINCTRL_PIN_42,
|
||||
PINCTRL_PIN_43,
|
||||
PINCTRL_PIN_44,
|
||||
PINCTRL_PIN_45,
|
||||
PINCTRL_PIN_46,
|
||||
PINCTRL_PIN_47,
|
||||
PINCTRL_PIN_48,
|
||||
PINCTRL_PIN_49,
|
||||
PINCTRL_PIN_50,
|
||||
PINCTRL_PIN_51,
|
||||
PINCTRL_PIN_52,
|
||||
PINCTRL_PIN_53,
|
||||
PINCTRL_PIN_54,
|
||||
PINCTRL_PIN_55,
|
||||
PINCTRL_PIN_56,
|
||||
PINCTRL_PIN_57,
|
||||
PINCTRL_PIN_58,
|
||||
PINCTRL_PIN_59,
|
||||
PINCTRL_PIN_60,
|
||||
PINCTRL_PIN_61,
|
||||
PINCTRL_PIN_62,
|
||||
PINCTRL_PIN_63,
|
||||
PINCTRL_PIN_64,
|
||||
PINCTRL_PIN_65,
|
||||
PINCTRL_PIN_66,
|
||||
PINCTRL_PIN_67,
|
||||
PINCTRL_PIN_68,
|
||||
PINCTRL_PIN_69,
|
||||
PINCTRL_PIN_70,
|
||||
PINCTRL_PIN_71,
|
||||
PINCTRL_PIN_72,
|
||||
PINCTRL_PIN_73,
|
||||
PINCTRL_PIN_74,
|
||||
PINCTRL_PIN_75,
|
||||
PINCTRL_PIN_76,
|
||||
PINCTRL_PIN_77,
|
||||
END_PINS,
|
||||
};
|
||||
|
||||
#define MAX_PIN (unsigned int)(END_PINS)
|
||||
|
||||
// pinctrl group ids
|
||||
enum {
|
||||
PINCTRL_GRP_ETHERNET0_0,
|
||||
PINCTRL_GRP_ETHERNET1_0,
|
||||
PINCTRL_GRP_ETHERNET2_0,
|
||||
PINCTRL_GRP_ETHERNET3_0,
|
||||
PINCTRL_GRP_GEMTSU0_0,
|
||||
PINCTRL_GRP_GEMTSU0_1,
|
||||
PINCTRL_GRP_GEMTSU0_2,
|
||||
PINCTRL_GRP_MDIO0_0,
|
||||
PINCTRL_GRP_MDIO1_0,
|
||||
PINCTRL_GRP_MDIO1_1,
|
||||
PINCTRL_GRP_MDIO2_0,
|
||||
PINCTRL_GRP_MDIO3_0,
|
||||
PINCTRL_GRP_QSPI0_0,
|
||||
PINCTRL_GRP_QSPI_SS,
|
||||
PINCTRL_GRP_QSPI_FBCLK,
|
||||
PINCTRL_GRP_SPI0_0,
|
||||
PINCTRL_GRP_SPI0_0_SS0,
|
||||
PINCTRL_GRP_SPI0_0_SS1,
|
||||
PINCTRL_GRP_SPI0_0_SS2,
|
||||
PINCTRL_GRP_SPI0_1,
|
||||
PINCTRL_GRP_SPI0_1_SS0,
|
||||
PINCTRL_GRP_SPI0_1_SS1,
|
||||
PINCTRL_GRP_SPI0_1_SS2,
|
||||
PINCTRL_GRP_SPI0_2,
|
||||
PINCTRL_GRP_SPI0_2_SS0,
|
||||
PINCTRL_GRP_SPI0_2_SS1,
|
||||
PINCTRL_GRP_SPI0_2_SS2,
|
||||
PINCTRL_GRP_SPI0_3,
|
||||
PINCTRL_GRP_SPI0_3_SS0,
|
||||
PINCTRL_GRP_SPI0_3_SS1,
|
||||
PINCTRL_GRP_SPI0_3_SS2,
|
||||
PINCTRL_GRP_SPI0_4,
|
||||
PINCTRL_GRP_SPI0_4_SS0,
|
||||
PINCTRL_GRP_SPI0_4_SS1,
|
||||
PINCTRL_GRP_SPI0_4_SS2,
|
||||
PINCTRL_GRP_SPI0_5,
|
||||
PINCTRL_GRP_SPI0_5_SS0,
|
||||
PINCTRL_GRP_SPI0_5_SS1,
|
||||
PINCTRL_GRP_SPI0_5_SS2,
|
||||
PINCTRL_GRP_SPI1_0,
|
||||
PINCTRL_GRP_SPI1_0_SS0,
|
||||
PINCTRL_GRP_SPI1_0_SS1,
|
||||
PINCTRL_GRP_SPI1_0_SS2,
|
||||
PINCTRL_GRP_SPI1_1,
|
||||
PINCTRL_GRP_SPI1_1_SS0,
|
||||
PINCTRL_GRP_SPI1_1_SS1,
|
||||
PINCTRL_GRP_SPI1_1_SS2,
|
||||
PINCTRL_GRP_SPI1_2,
|
||||
PINCTRL_GRP_SPI1_2_SS0,
|
||||
PINCTRL_GRP_SPI1_2_SS1,
|
||||
PINCTRL_GRP_SPI1_2_SS2,
|
||||
PINCTRL_GRP_SPI1_3,
|
||||
PINCTRL_GRP_SPI1_3_SS0,
|
||||
PINCTRL_GRP_SPI1_3_SS1,
|
||||
PINCTRL_GRP_SPI1_3_SS2,
|
||||
PINCTRL_GRP_SPI1_4,
|
||||
PINCTRL_GRP_SPI1_4_SS0,
|
||||
PINCTRL_GRP_SPI1_4_SS1,
|
||||
PINCTRL_GRP_SPI1_4_SS2,
|
||||
PINCTRL_GRP_SPI1_5,
|
||||
PINCTRL_GRP_SPI1_5_SS0,
|
||||
PINCTRL_GRP_SPI1_5_SS1,
|
||||
PINCTRL_GRP_SPI1_5_SS2,
|
||||
PINCTRL_GRP_SDIO0_0,
|
||||
PINCTRL_GRP_SDIO0_1,
|
||||
PINCTRL_GRP_SDIO0_2,
|
||||
PINCTRL_GRP_SDIO0_4BIT_0_0,
|
||||
PINCTRL_GRP_SDIO0_4BIT_0_1,
|
||||
PINCTRL_GRP_SDIO0_4BIT_1_0,
|
||||
PINCTRL_GRP_SDIO0_4BIT_1_1,
|
||||
PINCTRL_GRP_SDIO0_4BIT_2_0,
|
||||
PINCTRL_GRP_SDIO0_4BIT_2_1,
|
||||
PINCTRL_GRP_SDIO0_1BIT_0_0,
|
||||
PINCTRL_GRP_SDIO0_1BIT_0_1,
|
||||
PINCTRL_GRP_SDIO0_1BIT_0_2,
|
||||
PINCTRL_GRP_SDIO0_1BIT_0_3,
|
||||
PINCTRL_GRP_SDIO0_1BIT_0_4,
|
||||
PINCTRL_GRP_SDIO0_1BIT_0_5,
|
||||
PINCTRL_GRP_SDIO0_1BIT_0_6,
|
||||
PINCTRL_GRP_SDIO0_1BIT_0_7,
|
||||
PINCTRL_GRP_SDIO0_1BIT_1_0,
|
||||
PINCTRL_GRP_SDIO0_1BIT_1_1,
|
||||
PINCTRL_GRP_SDIO0_1BIT_1_2,
|
||||
PINCTRL_GRP_SDIO0_1BIT_1_3,
|
||||
PINCTRL_GRP_SDIO0_1BIT_1_4,
|
||||
PINCTRL_GRP_SDIO0_1BIT_1_5,
|
||||
PINCTRL_GRP_SDIO0_1BIT_1_6,
|
||||
PINCTRL_GRP_SDIO0_1BIT_1_7,
|
||||
PINCTRL_GRP_SDIO0_1BIT_2_0,
|
||||
PINCTRL_GRP_SDIO0_1BIT_2_1,
|
||||
PINCTRL_GRP_SDIO0_1BIT_2_2,
|
||||
PINCTRL_GRP_SDIO0_1BIT_2_3,
|
||||
PINCTRL_GRP_SDIO0_1BIT_2_4,
|
||||
PINCTRL_GRP_SDIO0_1BIT_2_5,
|
||||
PINCTRL_GRP_SDIO0_1BIT_2_6,
|
||||
PINCTRL_GRP_SDIO0_1BIT_2_7,
|
||||
PINCTRL_GRP_SDIO0_0_PC,
|
||||
PINCTRL_GRP_SDIO0_0_CD,
|
||||
PINCTRL_GRP_SDIO0_0_WP,
|
||||
PINCTRL_GRP_SDIO0_1_PC,
|
||||
PINCTRL_GRP_SDIO0_1_CD,
|
||||
PINCTRL_GRP_SDIO0_1_WP,
|
||||
PINCTRL_GRP_SDIO0_2_PC,
|
||||
PINCTRL_GRP_SDIO0_2_CD,
|
||||
PINCTRL_GRP_SDIO0_2_WP,
|
||||
PINCTRL_GRP_SDIO1_0,
|
||||
PINCTRL_GRP_SDIO1_4BIT_0_0,
|
||||
PINCTRL_GRP_SDIO1_4BIT_0_1,
|
||||
PINCTRL_GRP_SDIO1_4BIT_1_0,
|
||||
PINCTRL_GRP_SDIO1_1BIT_0_0,
|
||||
PINCTRL_GRP_SDIO1_1BIT_0_1,
|
||||
PINCTRL_GRP_SDIO1_1BIT_0_2,
|
||||
PINCTRL_GRP_SDIO1_1BIT_0_3,
|
||||
PINCTRL_GRP_SDIO1_1BIT_0_4,
|
||||
PINCTRL_GRP_SDIO1_1BIT_0_5,
|
||||
PINCTRL_GRP_SDIO1_1BIT_0_6,
|
||||
PINCTRL_GRP_SDIO1_1BIT_0_7,
|
||||
PINCTRL_GRP_SDIO1_1BIT_1_0,
|
||||
PINCTRL_GRP_SDIO1_1BIT_1_1,
|
||||
PINCTRL_GRP_SDIO1_1BIT_1_2,
|
||||
PINCTRL_GRP_SDIO1_1BIT_1_3,
|
||||
PINCTRL_GRP_SDIO1_0_PC,
|
||||
PINCTRL_GRP_SDIO1_0_CD,
|
||||
PINCTRL_GRP_SDIO1_0_WP,
|
||||
PINCTRL_GRP_SDIO1_1_PC,
|
||||
PINCTRL_GRP_SDIO1_1_CD,
|
||||
PINCTRL_GRP_SDIO1_1_WP,
|
||||
PINCTRL_GRP_NAND0_0,
|
||||
PINCTRL_GRP_NAND0_0_CE,
|
||||
PINCTRL_GRP_NAND0_0_RB,
|
||||
PINCTRL_GRP_NAND0_0_DQS,
|
||||
PINCTRL_GRP_NAND0_1_CE,
|
||||
PINCTRL_GRP_NAND0_1_RB,
|
||||
PINCTRL_GRP_NAND0_1_DQS,
|
||||
PINCTRL_GRP_CAN0_0,
|
||||
PINCTRL_GRP_CAN0_1,
|
||||
PINCTRL_GRP_CAN0_2,
|
||||
PINCTRL_GRP_CAN0_3,
|
||||
PINCTRL_GRP_CAN0_4,
|
||||
PINCTRL_GRP_CAN0_5,
|
||||
PINCTRL_GRP_CAN0_6,
|
||||
PINCTRL_GRP_CAN0_7,
|
||||
PINCTRL_GRP_CAN0_8,
|
||||
PINCTRL_GRP_CAN0_9,
|
||||
PINCTRL_GRP_CAN0_10,
|
||||
PINCTRL_GRP_CAN0_11,
|
||||
PINCTRL_GRP_CAN0_12,
|
||||
PINCTRL_GRP_CAN0_13,
|
||||
PINCTRL_GRP_CAN0_14,
|
||||
PINCTRL_GRP_CAN0_15,
|
||||
PINCTRL_GRP_CAN0_16,
|
||||
PINCTRL_GRP_CAN0_17,
|
||||
PINCTRL_GRP_CAN0_18,
|
||||
PINCTRL_GRP_CAN1_0,
|
||||
PINCTRL_GRP_CAN1_1,
|
||||
PINCTRL_GRP_CAN1_2,
|
||||
PINCTRL_GRP_CAN1_3,
|
||||
PINCTRL_GRP_CAN1_4,
|
||||
PINCTRL_GRP_CAN1_5,
|
||||
PINCTRL_GRP_CAN1_6,
|
||||
PINCTRL_GRP_CAN1_7,
|
||||
PINCTRL_GRP_CAN1_8,
|
||||
PINCTRL_GRP_CAN1_9,
|
||||
PINCTRL_GRP_CAN1_10,
|
||||
PINCTRL_GRP_CAN1_11,
|
||||
PINCTRL_GRP_CAN1_12,
|
||||
PINCTRL_GRP_CAN1_13,
|
||||
PINCTRL_GRP_CAN1_14,
|
||||
PINCTRL_GRP_CAN1_15,
|
||||
PINCTRL_GRP_CAN1_16,
|
||||
PINCTRL_GRP_CAN1_17,
|
||||
PINCTRL_GRP_CAN1_18,
|
||||
PINCTRL_GRP_CAN1_19,
|
||||
PINCTRL_GRP_UART0_0,
|
||||
PINCTRL_GRP_UART0_1,
|
||||
PINCTRL_GRP_UART0_2,
|
||||
PINCTRL_GRP_UART0_3,
|
||||
PINCTRL_GRP_UART0_4,
|
||||
PINCTRL_GRP_UART0_5,
|
||||
PINCTRL_GRP_UART0_6,
|
||||
PINCTRL_GRP_UART0_7,
|
||||
PINCTRL_GRP_UART0_8,
|
||||
PINCTRL_GRP_UART0_9,
|
||||
PINCTRL_GRP_UART0_10,
|
||||
PINCTRL_GRP_UART0_11,
|
||||
PINCTRL_GRP_UART0_12,
|
||||
PINCTRL_GRP_UART0_13,
|
||||
PINCTRL_GRP_UART0_14,
|
||||
PINCTRL_GRP_UART0_15,
|
||||
PINCTRL_GRP_UART0_16,
|
||||
PINCTRL_GRP_UART0_17,
|
||||
PINCTRL_GRP_UART0_18,
|
||||
PINCTRL_GRP_UART1_0,
|
||||
PINCTRL_GRP_UART1_1,
|
||||
PINCTRL_GRP_UART1_2,
|
||||
PINCTRL_GRP_UART1_3,
|
||||
PINCTRL_GRP_UART1_4,
|
||||
PINCTRL_GRP_UART1_5,
|
||||
PINCTRL_GRP_UART1_6,
|
||||
PINCTRL_GRP_UART1_7,
|
||||
PINCTRL_GRP_UART1_8,
|
||||
PINCTRL_GRP_UART1_9,
|
||||
PINCTRL_GRP_UART1_10,
|
||||
PINCTRL_GRP_UART1_11,
|
||||
PINCTRL_GRP_UART1_12,
|
||||
PINCTRL_GRP_UART1_13,
|
||||
PINCTRL_GRP_UART1_14,
|
||||
PINCTRL_GRP_UART1_15,
|
||||
PINCTRL_GRP_UART1_16,
|
||||
PINCTRL_GRP_UART1_17,
|
||||
PINCTRL_GRP_UART1_18,
|
||||
PINCTRL_GRP_I2C0_0,
|
||||
PINCTRL_GRP_I2C0_1,
|
||||
PINCTRL_GRP_I2C0_2,
|
||||
PINCTRL_GRP_I2C0_3,
|
||||
PINCTRL_GRP_I2C0_4,
|
||||
PINCTRL_GRP_I2C0_5,
|
||||
PINCTRL_GRP_I2C0_6,
|
||||
PINCTRL_GRP_I2C0_7,
|
||||
PINCTRL_GRP_I2C0_8,
|
||||
PINCTRL_GRP_I2C0_9,
|
||||
PINCTRL_GRP_I2C0_10,
|
||||
PINCTRL_GRP_I2C0_11,
|
||||
PINCTRL_GRP_I2C0_12,
|
||||
PINCTRL_GRP_I2C0_13,
|
||||
PINCTRL_GRP_I2C0_14,
|
||||
PINCTRL_GRP_I2C0_15,
|
||||
PINCTRL_GRP_I2C0_16,
|
||||
PINCTRL_GRP_I2C0_17,
|
||||
PINCTRL_GRP_I2C0_18,
|
||||
PINCTRL_GRP_I2C1_0,
|
||||
PINCTRL_GRP_I2C1_1,
|
||||
PINCTRL_GRP_I2C1_2,
|
||||
PINCTRL_GRP_I2C1_3,
|
||||
PINCTRL_GRP_I2C1_4,
|
||||
PINCTRL_GRP_I2C1_5,
|
||||
PINCTRL_GRP_I2C1_6,
|
||||
PINCTRL_GRP_I2C1_7,
|
||||
PINCTRL_GRP_I2C1_8,
|
||||
PINCTRL_GRP_I2C1_9,
|
||||
PINCTRL_GRP_I2C1_10,
|
||||
PINCTRL_GRP_I2C1_11,
|
||||
PINCTRL_GRP_I2C1_12,
|
||||
PINCTRL_GRP_I2C1_13,
|
||||
PINCTRL_GRP_I2C1_14,
|
||||
PINCTRL_GRP_I2C1_15,
|
||||
PINCTRL_GRP_I2C1_16,
|
||||
PINCTRL_GRP_I2C1_17,
|
||||
PINCTRL_GRP_I2C1_18,
|
||||
PINCTRL_GRP_I2C1_19,
|
||||
PINCTRL_GRP_TTC0_0_CLK,
|
||||
PINCTRL_GRP_TTC0_0_WAV,
|
||||
PINCTRL_GRP_TTC0_1_CLK,
|
||||
PINCTRL_GRP_TTC0_1_WAV,
|
||||
PINCTRL_GRP_TTC0_2_CLK,
|
||||
PINCTRL_GRP_TTC0_2_WAV,
|
||||
PINCTRL_GRP_TTC0_3_CLK,
|
||||
PINCTRL_GRP_TTC0_3_WAV,
|
||||
PINCTRL_GRP_TTC0_4_CLK,
|
||||
PINCTRL_GRP_TTC0_4_WAV,
|
||||
PINCTRL_GRP_TTC0_5_CLK,
|
||||
PINCTRL_GRP_TTC0_5_WAV,
|
||||
PINCTRL_GRP_TTC0_6_CLK,
|
||||
PINCTRL_GRP_TTC0_6_WAV,
|
||||
PINCTRL_GRP_TTC0_7_CLK,
|
||||
PINCTRL_GRP_TTC0_7_WAV,
|
||||
PINCTRL_GRP_TTC0_8_CLK,
|
||||
PINCTRL_GRP_TTC0_8_WAV,
|
||||
PINCTRL_GRP_TTC1_0_CLK,
|
||||
PINCTRL_GRP_TTC1_0_WAV,
|
||||
PINCTRL_GRP_TTC1_1_CLK,
|
||||
PINCTRL_GRP_TTC1_1_WAV,
|
||||
PINCTRL_GRP_TTC1_2_CLK,
|
||||
PINCTRL_GRP_TTC1_2_WAV,
|
||||
PINCTRL_GRP_TTC1_3_CLK,
|
||||
PINCTRL_GRP_TTC1_3_WAV,
|
||||
PINCTRL_GRP_TTC1_4_CLK,
|
||||
PINCTRL_GRP_TTC1_4_WAV,
|
||||
PINCTRL_GRP_TTC1_5_CLK,
|
||||
PINCTRL_GRP_TTC1_5_WAV,
|
||||
PINCTRL_GRP_TTC1_6_CLK,
|
||||
PINCTRL_GRP_TTC1_6_WAV,
|
||||
PINCTRL_GRP_TTC1_7_CLK,
|
||||
PINCTRL_GRP_TTC1_7_WAV,
|
||||
PINCTRL_GRP_TTC1_8_CLK,
|
||||
PINCTRL_GRP_TTC1_8_WAV,
|
||||
PINCTRL_GRP_TTC2_0_CLK,
|
||||
PINCTRL_GRP_TTC2_0_WAV,
|
||||
PINCTRL_GRP_TTC2_1_CLK,
|
||||
PINCTRL_GRP_TTC2_1_WAV,
|
||||
PINCTRL_GRP_TTC2_2_CLK,
|
||||
PINCTRL_GRP_TTC2_2_WAV,
|
||||
PINCTRL_GRP_TTC2_3_CLK,
|
||||
PINCTRL_GRP_TTC2_3_WAV,
|
||||
PINCTRL_GRP_TTC2_4_CLK,
|
||||
PINCTRL_GRP_TTC2_4_WAV,
|
||||
PINCTRL_GRP_TTC2_5_CLK,
|
||||
PINCTRL_GRP_TTC2_5_WAV,
|
||||
PINCTRL_GRP_TTC2_6_CLK,
|
||||
PINCTRL_GRP_TTC2_6_WAV,
|
||||
PINCTRL_GRP_TTC2_7_CLK,
|
||||
PINCTRL_GRP_TTC2_7_WAV,
|
||||
PINCTRL_GRP_TTC2_8_CLK,
|
||||
PINCTRL_GRP_TTC2_8_WAV,
|
||||
PINCTRL_GRP_TTC3_0_CLK,
|
||||
PINCTRL_GRP_TTC3_0_WAV,
|
||||
PINCTRL_GRP_TTC3_1_CLK,
|
||||
PINCTRL_GRP_TTC3_1_WAV,
|
||||
PINCTRL_GRP_TTC3_2_CLK,
|
||||
PINCTRL_GRP_TTC3_2_WAV,
|
||||
PINCTRL_GRP_TTC3_3_CLK,
|
||||
PINCTRL_GRP_TTC3_3_WAV,
|
||||
PINCTRL_GRP_TTC3_4_CLK,
|
||||
PINCTRL_GRP_TTC3_4_WAV,
|
||||
PINCTRL_GRP_TTC3_5_CLK,
|
||||
PINCTRL_GRP_TTC3_5_WAV,
|
||||
PINCTRL_GRP_TTC3_6_CLK,
|
||||
PINCTRL_GRP_TTC3_6_WAV,
|
||||
PINCTRL_GRP_TTC3_7_CLK,
|
||||
PINCTRL_GRP_TTC3_7_WAV,
|
||||
PINCTRL_GRP_TTC3_8_CLK,
|
||||
PINCTRL_GRP_TTC3_8_WAV,
|
||||
PINCTRL_GRP_SWDT0_0_CLK,
|
||||
PINCTRL_GRP_SWDT0_0_RST,
|
||||
PINCTRL_GRP_SWDT0_1_CLK,
|
||||
PINCTRL_GRP_SWDT0_1_RST,
|
||||
PINCTRL_GRP_SWDT0_2_CLK,
|
||||
PINCTRL_GRP_SWDT0_2_RST,
|
||||
PINCTRL_GRP_SWDT0_3_CLK,
|
||||
PINCTRL_GRP_SWDT0_3_RST,
|
||||
PINCTRL_GRP_SWDT0_4_CLK,
|
||||
PINCTRL_GRP_SWDT0_4_RST,
|
||||
PINCTRL_GRP_SWDT0_5_CLK,
|
||||
PINCTRL_GRP_SWDT0_5_RST,
|
||||
PINCTRL_GRP_SWDT0_6_CLK,
|
||||
PINCTRL_GRP_SWDT0_6_RST,
|
||||
PINCTRL_GRP_SWDT0_7_CLK,
|
||||
PINCTRL_GRP_SWDT0_7_RST,
|
||||
PINCTRL_GRP_SWDT0_8_CLK,
|
||||
PINCTRL_GRP_SWDT0_8_RST,
|
||||
PINCTRL_GRP_SWDT0_9_CLK,
|
||||
PINCTRL_GRP_SWDT0_9_RST,
|
||||
PINCTRL_GRP_SWDT0_10_CLK,
|
||||
PINCTRL_GRP_SWDT0_10_RST,
|
||||
PINCTRL_GRP_SWDT0_11_CLK,
|
||||
PINCTRL_GRP_SWDT0_11_RST,
|
||||
PINCTRL_GRP_SWDT0_12_CLK,
|
||||
PINCTRL_GRP_SWDT0_12_RST,
|
||||
PINCTRL_GRP_SWDT1_0_CLK,
|
||||
PINCTRL_GRP_SWDT1_0_RST,
|
||||
PINCTRL_GRP_SWDT1_1_CLK,
|
||||
PINCTRL_GRP_SWDT1_1_RST,
|
||||
PINCTRL_GRP_SWDT1_2_CLK,
|
||||
PINCTRL_GRP_SWDT1_2_RST,
|
||||
PINCTRL_GRP_SWDT1_3_CLK,
|
||||
PINCTRL_GRP_SWDT1_3_RST,
|
||||
PINCTRL_GRP_SWDT1_4_CLK,
|
||||
PINCTRL_GRP_SWDT1_4_RST,
|
||||
PINCTRL_GRP_SWDT1_5_CLK,
|
||||
PINCTRL_GRP_SWDT1_5_RST,
|
||||
PINCTRL_GRP_SWDT1_6_CLK,
|
||||
PINCTRL_GRP_SWDT1_6_RST,
|
||||
PINCTRL_GRP_SWDT1_7_CLK,
|
||||
PINCTRL_GRP_SWDT1_7_RST,
|
||||
PINCTRL_GRP_SWDT1_8_CLK,
|
||||
PINCTRL_GRP_SWDT1_8_RST,
|
||||
PINCTRL_GRP_SWDT1_9_CLK,
|
||||
PINCTRL_GRP_SWDT1_9_RST,
|
||||
PINCTRL_GRP_SWDT1_10_CLK,
|
||||
PINCTRL_GRP_SWDT1_10_RST,
|
||||
PINCTRL_GRP_SWDT1_11_CLK,
|
||||
PINCTRL_GRP_SWDT1_11_RST,
|
||||
PINCTRL_GRP_SWDT1_12_CLK,
|
||||
PINCTRL_GRP_SWDT1_12_RST,
|
||||
PINCTRL_GRP_GPIO0_0,
|
||||
PINCTRL_GRP_GPIO0_1,
|
||||
PINCTRL_GRP_GPIO0_2,
|
||||
PINCTRL_GRP_GPIO0_3,
|
||||
PINCTRL_GRP_GPIO0_4,
|
||||
PINCTRL_GRP_GPIO0_5,
|
||||
PINCTRL_GRP_GPIO0_6,
|
||||
PINCTRL_GRP_GPIO0_7,
|
||||
PINCTRL_GRP_GPIO0_8,
|
||||
PINCTRL_GRP_GPIO0_9,
|
||||
PINCTRL_GRP_GPIO0_10,
|
||||
PINCTRL_GRP_GPIO0_11,
|
||||
PINCTRL_GRP_GPIO0_12,
|
||||
PINCTRL_GRP_GPIO0_13,
|
||||
PINCTRL_GRP_GPIO0_14,
|
||||
PINCTRL_GRP_GPIO0_15,
|
||||
PINCTRL_GRP_GPIO0_16,
|
||||
PINCTRL_GRP_GPIO0_17,
|
||||
PINCTRL_GRP_GPIO0_18,
|
||||
PINCTRL_GRP_GPIO0_19,
|
||||
PINCTRL_GRP_GPIO0_20,
|
||||
PINCTRL_GRP_GPIO0_21,
|
||||
PINCTRL_GRP_GPIO0_22,
|
||||
PINCTRL_GRP_GPIO0_23,
|
||||
PINCTRL_GRP_GPIO0_24,
|
||||
PINCTRL_GRP_GPIO0_25,
|
||||
PINCTRL_GRP_GPIO0_26,
|
||||
PINCTRL_GRP_GPIO0_27,
|
||||
PINCTRL_GRP_GPIO0_28,
|
||||
PINCTRL_GRP_GPIO0_29,
|
||||
PINCTRL_GRP_GPIO0_30,
|
||||
PINCTRL_GRP_GPIO0_31,
|
||||
PINCTRL_GRP_GPIO0_32,
|
||||
PINCTRL_GRP_GPIO0_33,
|
||||
PINCTRL_GRP_GPIO0_34,
|
||||
PINCTRL_GRP_GPIO0_35,
|
||||
PINCTRL_GRP_GPIO0_36,
|
||||
PINCTRL_GRP_GPIO0_37,
|
||||
PINCTRL_GRP_GPIO0_38,
|
||||
PINCTRL_GRP_GPIO0_39,
|
||||
PINCTRL_GRP_GPIO0_40,
|
||||
PINCTRL_GRP_GPIO0_41,
|
||||
PINCTRL_GRP_GPIO0_42,
|
||||
PINCTRL_GRP_GPIO0_43,
|
||||
PINCTRL_GRP_GPIO0_44,
|
||||
PINCTRL_GRP_GPIO0_45,
|
||||
PINCTRL_GRP_GPIO0_46,
|
||||
PINCTRL_GRP_GPIO0_47,
|
||||
PINCTRL_GRP_GPIO0_48,
|
||||
PINCTRL_GRP_GPIO0_49,
|
||||
PINCTRL_GRP_GPIO0_50,
|
||||
PINCTRL_GRP_GPIO0_51,
|
||||
PINCTRL_GRP_GPIO0_52,
|
||||
PINCTRL_GRP_GPIO0_53,
|
||||
PINCTRL_GRP_GPIO0_54,
|
||||
PINCTRL_GRP_GPIO0_55,
|
||||
PINCTRL_GRP_GPIO0_56,
|
||||
PINCTRL_GRP_GPIO0_57,
|
||||
PINCTRL_GRP_GPIO0_58,
|
||||
PINCTRL_GRP_GPIO0_59,
|
||||
PINCTRL_GRP_GPIO0_60,
|
||||
PINCTRL_GRP_GPIO0_61,
|
||||
PINCTRL_GRP_GPIO0_62,
|
||||
PINCTRL_GRP_GPIO0_63,
|
||||
PINCTRL_GRP_GPIO0_64,
|
||||
PINCTRL_GRP_GPIO0_65,
|
||||
PINCTRL_GRP_GPIO0_66,
|
||||
PINCTRL_GRP_GPIO0_67,
|
||||
PINCTRL_GRP_GPIO0_68,
|
||||
PINCTRL_GRP_GPIO0_69,
|
||||
PINCTRL_GRP_GPIO0_70,
|
||||
PINCTRL_GRP_GPIO0_71,
|
||||
PINCTRL_GRP_GPIO0_72,
|
||||
PINCTRL_GRP_GPIO0_73,
|
||||
PINCTRL_GRP_GPIO0_74,
|
||||
PINCTRL_GRP_GPIO0_75,
|
||||
PINCTRL_GRP_GPIO0_76,
|
||||
PINCTRL_GRP_GPIO0_77,
|
||||
PINCTRL_GRP_USB0_0,
|
||||
PINCTRL_GRP_USB1_0,
|
||||
PINCTRL_GRP_PMU0_0,
|
||||
PINCTRL_GRP_PMU0_1,
|
||||
PINCTRL_GRP_PMU0_2,
|
||||
PINCTRL_GRP_PMU0_3,
|
||||
PINCTRL_GRP_PMU0_4,
|
||||
PINCTRL_GRP_PMU0_5,
|
||||
PINCTRL_GRP_PMU0_6,
|
||||
PINCTRL_GRP_PMU0_7,
|
||||
PINCTRL_GRP_PMU0_8,
|
||||
PINCTRL_GRP_PMU0_9,
|
||||
PINCTRL_GRP_PMU0_10,
|
||||
PINCTRL_GRP_PMU0_11,
|
||||
PINCTRL_GRP_PCIE0_0,
|
||||
PINCTRL_GRP_PCIE0_1,
|
||||
PINCTRL_GRP_PCIE0_2,
|
||||
PINCTRL_GRP_PCIE0_3,
|
||||
PINCTRL_GRP_PCIE0_4,
|
||||
PINCTRL_GRP_PCIE0_5,
|
||||
PINCTRL_GRP_PCIE0_6,
|
||||
PINCTRL_GRP_PCIE0_7,
|
||||
PINCTRL_GRP_CSU0_0,
|
||||
PINCTRL_GRP_CSU0_1,
|
||||
PINCTRL_GRP_CSU0_2,
|
||||
PINCTRL_GRP_CSU0_3,
|
||||
PINCTRL_GRP_CSU0_4,
|
||||
PINCTRL_GRP_CSU0_5,
|
||||
PINCTRL_GRP_CSU0_6,
|
||||
PINCTRL_GRP_CSU0_7,
|
||||
PINCTRL_GRP_CSU0_8,
|
||||
PINCTRL_GRP_CSU0_9,
|
||||
PINCTRL_GRP_CSU0_10,
|
||||
PINCTRL_GRP_CSU0_11,
|
||||
PINCTRL_GRP_DPAUX0_0,
|
||||
PINCTRL_GRP_DPAUX0_1,
|
||||
PINCTRL_GRP_DPAUX0_2,
|
||||
PINCTRL_GRP_DPAUX0_3,
|
||||
PINCTRL_GRP_PJTAG0_0,
|
||||
PINCTRL_GRP_PJTAG0_1,
|
||||
PINCTRL_GRP_PJTAG0_2,
|
||||
PINCTRL_GRP_PJTAG0_3,
|
||||
PINCTRL_GRP_PJTAG0_4,
|
||||
PINCTRL_GRP_PJTAG0_5,
|
||||
PINCTRL_GRP_TRACE0_0,
|
||||
PINCTRL_GRP_TRACE0_0_CLK,
|
||||
PINCTRL_GRP_TRACE0_1,
|
||||
PINCTRL_GRP_TRACE0_1_CLK,
|
||||
PINCTRL_GRP_TRACE0_2,
|
||||
PINCTRL_GRP_TRACE0_2_CLK,
|
||||
PINCTRL_GRP_TESTSCAN0_0,
|
||||
};
|
||||
|
||||
// pinctrl config parameters
|
||||
enum {
|
||||
PINCTRL_CONFIG_SLEW_RATE,
|
||||
PINCTRL_CONFIG_BIAS_STATUS,
|
||||
PINCTRL_CONFIG_PULL_CTRL,
|
||||
PINCTRL_CONFIG_SCHMITT_CMOS,
|
||||
PINCTRL_CONFIG_DRIVE_STRENGTH,
|
||||
PINCTRL_CONFIG_VOLTAGE_STATUS,
|
||||
PINCTRL_CONFIG_MAX,
|
||||
};
|
||||
|
||||
// pinctrl slew rate
|
||||
#define PINCTRL_SLEW_RATE_FAST 0U
|
||||
#define PINCTRL_SLEW_RATE_SLOW 1U
|
||||
|
||||
// pinctrl bias status
|
||||
#define PINCTRL_BIAS_DISABLE 0U
|
||||
#define PINCTRL_BIAS_ENABLE 1U
|
||||
|
||||
// pinctrl pull control
|
||||
#define PINCTRL_BIAS_PULL_DOWN 0U
|
||||
#define PINCTRL_BIAS_PULL_UP 1U
|
||||
|
||||
// pinctrl schmitt cmos type
|
||||
#define PINCTRL_INPUT_TYPE_CMOS 0U
|
||||
#define PINCTRL_INPUT_TYPE_SCHMITT 1U
|
||||
|
||||
//pinctrl drive strength values
|
||||
#define PINCTRL_DRIVE_STRENGTH_2MA 0U
|
||||
#define PINCTRL_DRIVE_STRENGTH_4MA 1U
|
||||
#define PINCTRL_DRIVE_STRENGTH_8MA 2U
|
||||
#define PINCTRL_DRIVE_STRENGTH_12MA 3U
|
||||
|
||||
enum pm_ret_status pm_api_pinctrl_set_function(unsigned int pin,
|
||||
unsigned int fid);
|
||||
enum pm_ret_status pm_api_pinctrl_get_function(unsigned int pin,
|
||||
unsigned int *id);
|
||||
enum pm_ret_status pm_api_pinctrl_set_config(unsigned int pin,
|
||||
unsigned int param,
|
||||
unsigned int value);
|
||||
enum pm_ret_status pm_api_pinctrl_get_config(unsigned int pin,
|
||||
unsigned int param,
|
||||
unsigned int *value);
|
||||
enum pm_ret_status pm_api_pinctrl_get_function_name(unsigned int fid,
|
||||
char *name);
|
||||
enum pm_ret_status pm_api_pinctrl_get_function_groups(unsigned int fid,
|
||||
unsigned int index,
|
||||
uint16_t *groups);
|
||||
enum pm_ret_status pm_api_pinctrl_get_pin_groups(unsigned int pin,
|
||||
unsigned int index,
|
||||
uint16_t *groups);
|
||||
enum pm_ret_status pm_api_pinctrl_get_num_pins(unsigned int *npins);
|
||||
enum pm_ret_status pm_api_pinctrl_get_num_functions(unsigned int *nfuncs);
|
||||
enum pm_ret_status pm_api_pinctrl_get_num_func_groups(unsigned int fid,
|
||||
unsigned int *ngroups);
|
||||
#endif /* _PM_API_PINCTRL_H_ */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -11,6 +11,9 @@
|
|||
|
||||
#include <arch_helpers.h>
|
||||
#include <platform.h>
|
||||
#include "pm_api_clock.h"
|
||||
#include "pm_api_ioctl.h"
|
||||
#include "pm_api_pinctrl.h"
|
||||
#include "pm_api_sys.h"
|
||||
#include "pm_client.h"
|
||||
#include "pm_common.h"
|
||||
|
|
@ -545,3 +548,529 @@ void pm_get_callbackdata(uint32_t *data, size_t count)
|
|||
pm_ipi_buff_read_callb(data, count);
|
||||
pm_ipi_irq_clear(primary_proc);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_request() - Request Pin from firmware
|
||||
* @pin Pin number to request
|
||||
*
|
||||
* This function requests pin from firmware.
|
||||
*
|
||||
* @return Returns status, either success or error+reason.
|
||||
*/
|
||||
enum pm_ret_status pm_pinctrl_request(unsigned int pin)
|
||||
{
|
||||
return PM_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_release() - Release Pin from firmware
|
||||
* @pin Pin number to release
|
||||
*
|
||||
* This function releases pin from firmware.
|
||||
*
|
||||
* @return Returns status, either success or error+reason.
|
||||
*/
|
||||
enum pm_ret_status pm_pinctrl_release(unsigned int pin)
|
||||
{
|
||||
return PM_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_get_function() - Read function id set for the given pin
|
||||
* @pin Pin number
|
||||
* @nid Node ID of function currently set for given pin
|
||||
*
|
||||
* This function provides the function currently set for the given pin.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
enum pm_ret_status pm_pinctrl_get_function(unsigned int pin,
|
||||
enum pm_node_id *nid)
|
||||
{
|
||||
return pm_api_pinctrl_get_function(pin, nid);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_set_function() - Set function id set for the given pin
|
||||
* @pin Pin number
|
||||
* @nid Node ID of function to set for given pin
|
||||
*
|
||||
* This function provides the function currently set for the given pin.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
enum pm_ret_status pm_pinctrl_set_function(unsigned int pin,
|
||||
enum pm_node_id nid)
|
||||
{
|
||||
return pm_api_pinctrl_set_function(pin, (unsigned int)nid);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_get_config() - Read value of requested config param for given pin
|
||||
* @pin Pin number
|
||||
* @param Parameter values to be read
|
||||
* @value Buffer for configuration Parameter value
|
||||
*
|
||||
* This function provides the configuration parameter value for the given pin.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
enum pm_ret_status pm_pinctrl_get_config(unsigned int pin,
|
||||
unsigned int param,
|
||||
unsigned int *value)
|
||||
{
|
||||
return pm_api_pinctrl_get_config(pin, param, value);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_set_config() - Read value of requested config param for given pin
|
||||
* @pin Pin number
|
||||
* @param Parameter to set
|
||||
* @value Parameter value to set
|
||||
*
|
||||
* This function provides the configuration parameter value for the given pin.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
enum pm_ret_status pm_pinctrl_set_config(unsigned int pin,
|
||||
unsigned int param,
|
||||
unsigned int value)
|
||||
{
|
||||
return pm_api_pinctrl_set_config(pin, param, value);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_ioctl() - PM IOCTL API for device control and configs
|
||||
* @node_id Node ID of the device
|
||||
* @ioctl_id ID of the requested IOCTL
|
||||
* @arg1 Argument 1 to requested IOCTL call
|
||||
* @arg2 Argument 2 to requested IOCTL call
|
||||
* @out Returned output value
|
||||
*
|
||||
* This function calls IOCTL to firmware for device control and configuration.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
enum pm_ret_status pm_ioctl(enum pm_node_id nid,
|
||||
unsigned int ioctl_id,
|
||||
unsigned int arg1,
|
||||
unsigned int arg2,
|
||||
unsigned int *value)
|
||||
{
|
||||
return pm_api_ioctl(nid, ioctl_id, arg1, arg2, value);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_clock_get_name() - PM call to request a clock's name
|
||||
* @clock_id Clock ID
|
||||
* @name Name of clock (max 16 bytes)
|
||||
*
|
||||
* This function is used by master to get nmae of clock specified
|
||||
* by given clock ID.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_clock_get_name(unsigned int clock_id, char *name)
|
||||
{
|
||||
return pm_api_clock_get_name(clock_id, name);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_clock_get_topology() - PM call to request a clock's topology
|
||||
* @clock_id Clock ID
|
||||
* @index Topology index for next toplogy node
|
||||
* @topology Buffer to store nodes in topology and flags
|
||||
*
|
||||
* This function is used by master to get topology information for the
|
||||
* clock specified by given clock ID. Each response would return 3
|
||||
* topology nodes. To get next nodes, caller needs to call this API with
|
||||
* index of next node. Index starts from 0.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_clock_get_topology(unsigned int clock_id,
|
||||
unsigned int index,
|
||||
uint32_t *topology)
|
||||
{
|
||||
return pm_api_clock_get_topology(clock_id, index, topology);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_clock_get_fixedfactor_params() - PM call to request a clock's fixed factor
|
||||
* parameters for fixed clock
|
||||
* @clock_id Clock ID
|
||||
* @mul Multiplication value
|
||||
* @div Divisor value
|
||||
*
|
||||
* This function is used by master to get fixed factor parameers for the
|
||||
* fixed clock. This API is application only for the fixed clock.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_clock_get_fixedfactor_params(unsigned int clock_id,
|
||||
uint32_t *mul,
|
||||
uint32_t *div)
|
||||
{
|
||||
return pm_api_clock_get_fixedfactor_params(clock_id, mul, div);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_clock_get_parents() - PM call to request a clock's first 3 parents
|
||||
* @clock_id Clock ID
|
||||
* @index Index of next parent
|
||||
* @parents Parents of the given clock
|
||||
*
|
||||
* This function is used by master to get clock's parents information.
|
||||
* This API will return 3 parents with a single response. To get other
|
||||
* parents, master should call same API in loop with new parent index
|
||||
* till error is returned.
|
||||
*
|
||||
* E.g First call should have index 0 which will return parents 0, 1 and
|
||||
* 2. Next call, index should be 3 which will return parent 3,4 and 5 and
|
||||
* so on.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_clock_get_parents(unsigned int clock_id,
|
||||
unsigned int index,
|
||||
uint32_t *parents)
|
||||
{
|
||||
return pm_api_clock_get_parents(clock_id, index, parents);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_clock_get_attributes() - PM call to request a clock's attributes
|
||||
* @clock_id Clock ID
|
||||
* @attr Clock attributes
|
||||
*
|
||||
* This function is used by master to get clock's attributes
|
||||
* (e.g. valid, clock type, etc).
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
static enum pm_ret_status pm_clock_get_attributes(unsigned int clock_id,
|
||||
uint32_t *attr)
|
||||
{
|
||||
return pm_api_clock_get_attributes(clock_id, attr);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_clock_enable() - Enable the clock for given id
|
||||
* @clock_id: Id of the clock to be enabled
|
||||
*
|
||||
* This function is used by master to enable the clock
|
||||
* including peripherals and PLL clocks.
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
|
||||
enum pm_ret_status pm_clock_enable(unsigned int clock_id)
|
||||
{
|
||||
return pm_api_clock_enable(clock_id);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_clock_disable - Disable the clock for given id
|
||||
* @clock_id: Id of the clock to be disable
|
||||
*
|
||||
* This function is used by master to disable the clock
|
||||
* including peripherals and PLL clocks.
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
|
||||
enum pm_ret_status pm_clock_disable(unsigned int clock_id)
|
||||
{
|
||||
return pm_api_clock_disable(clock_id);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_clock_getstate - Get the clock state for given id
|
||||
* @clock_id: Id of the clock to be queried
|
||||
* @state: 1/0 (Enabled/Disabled)
|
||||
*
|
||||
* This function is used by master to get the state of clock
|
||||
* including peripherals and PLL clocks.
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
enum pm_ret_status pm_clock_getstate(unsigned int clock_id,
|
||||
unsigned int *state)
|
||||
{
|
||||
return pm_api_clock_getstate(clock_id, state);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_clock_setdivider - Set the clock divider for given id
|
||||
* @clock_id: Id of the clock
|
||||
* @divider: divider value
|
||||
*
|
||||
* This function is used by master to set divider for any clock
|
||||
* to achieve desired rate.
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
enum pm_ret_status pm_clock_setdivider(unsigned int clock_id,
|
||||
unsigned int divider)
|
||||
{
|
||||
return pm_api_clock_setdivider(clock_id, divider);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_clock_getdivider - Get the clock divider for given id
|
||||
* @clock_id: Id of the clock
|
||||
* @divider: divider value
|
||||
*
|
||||
* This function is used by master to get divider values
|
||||
* for any clock.
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
enum pm_ret_status pm_clock_getdivider(unsigned int clock_id,
|
||||
unsigned int *divider)
|
||||
{
|
||||
return pm_api_clock_getdivider(clock_id, divider);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_clock_setrate - Set the clock rate for given id
|
||||
* @clock_id: Id of the clock
|
||||
* @rate: rate value in hz
|
||||
*
|
||||
* This function is used by master to set rate for any clock.
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
enum pm_ret_status pm_clock_setrate(unsigned int clock_id,
|
||||
uint64_t rate)
|
||||
{
|
||||
return pm_api_clock_setrate(clock_id, rate);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_clock_getrate - Get the clock rate for given id
|
||||
* @clock_id: Id of the clock
|
||||
* @rate: rate value in hz
|
||||
*
|
||||
* This function is used by master to get rate
|
||||
* for any clock.
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
enum pm_ret_status pm_clock_getrate(unsigned int clock_id,
|
||||
uint64_t *rate)
|
||||
{
|
||||
return pm_api_clock_getrate(clock_id, rate);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_clock_setparent - Set the clock parent for given id
|
||||
* @clock_id: Id of the clock
|
||||
* @parent_id: parent id
|
||||
*
|
||||
* This function is used by master to set parent for any clock.
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
enum pm_ret_status pm_clock_setparent(unsigned int clock_id,
|
||||
unsigned int parent_id)
|
||||
{
|
||||
return pm_api_clock_setparent(clock_id, parent_id);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_clock_getparent - Get the clock parent for given id
|
||||
* @clock_id: Id of the clock
|
||||
* @parent_id: parent id
|
||||
*
|
||||
* This function is used by master to get parent index
|
||||
* for any clock.
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
enum pm_ret_status pm_clock_getparent(unsigned int clock_id,
|
||||
unsigned int *parent_id)
|
||||
{
|
||||
return pm_api_clock_getparent(clock_id, parent_id);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_get_num_pins - PM call to request number of pins
|
||||
* @npins: Number of pins
|
||||
*
|
||||
* This function is used by master to get number of pins
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
static enum pm_ret_status pm_pinctrl_get_num_pins(uint32_t *npins)
|
||||
{
|
||||
return pm_api_pinctrl_get_num_pins(npins);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_get_num_functions - PM call to request number of functions
|
||||
* @nfuncs: Number of functions
|
||||
*
|
||||
* This function is used by master to get number of functions
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
static enum pm_ret_status pm_pinctrl_get_num_functions(uint32_t *nfuncs)
|
||||
{
|
||||
return pm_api_pinctrl_get_num_functions(nfuncs);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_get_num_function_groups - PM call to request number of
|
||||
* function groups
|
||||
* @fid: Id of function
|
||||
* @ngroups: Number of function groups
|
||||
*
|
||||
* This function is used by master to get number of function groups specified
|
||||
* by given function Id
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
static enum pm_ret_status pm_pinctrl_get_num_function_groups(unsigned int fid,
|
||||
uint32_t *ngroups)
|
||||
{
|
||||
return pm_api_pinctrl_get_num_func_groups(fid, ngroups);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_get_function_name - PM call to request function name
|
||||
* @fid: Id of function
|
||||
* @name: Name of function
|
||||
*
|
||||
* This function is used by master to get name of function specified
|
||||
* by given function Id
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
static enum pm_ret_status pm_pinctrl_get_function_name(unsigned int fid,
|
||||
char *name)
|
||||
{
|
||||
return pm_api_pinctrl_get_function_name(fid, name);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_get_function_groups - PM call to request function groups
|
||||
* @fid: Id of function
|
||||
* @index: Index of next function groups
|
||||
* @groups: Function groups
|
||||
*
|
||||
* This function is used by master to get function groups specified
|
||||
* by given function Id. This API will return 6 function groups with
|
||||
* a single response. To get other function groups, master should call
|
||||
* same API in loop with new function groups index till error is returned.
|
||||
*
|
||||
* E.g First call should have index 0 which will return function groups
|
||||
* 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return
|
||||
* function groups 6, 7, 8, 9, 10 and 11 and so on.
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
static enum pm_ret_status pm_pinctrl_get_function_groups(unsigned int fid,
|
||||
unsigned int index,
|
||||
uint16_t *groups)
|
||||
{
|
||||
return pm_api_pinctrl_get_function_groups(fid, index, groups);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_get_pin_groups - PM call to request pin groups
|
||||
* @pin_id: Id of pin
|
||||
* @index: Index of next pin groups
|
||||
* @groups: pin groups
|
||||
*
|
||||
* This function is used by master to get pin groups specified
|
||||
* by given pin Id. This API will return 6 pin groups with
|
||||
* a single response. To get other pin groups, master should call
|
||||
* same API in loop with new pin groups index till error is returned.
|
||||
*
|
||||
* E.g First call should have index 0 which will return pin groups
|
||||
* 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return
|
||||
* pin groups 6, 7, 8, 9, 10 and 11 and so on.
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
static enum pm_ret_status pm_pinctrl_get_pin_groups(unsigned int pin_id,
|
||||
unsigned int index,
|
||||
uint16_t *groups)
|
||||
{
|
||||
return pm_api_pinctrl_get_pin_groups(pin_id, index, groups);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_query_data() - PM API for querying firmware data
|
||||
* @arg1 Argument 1 to requested IOCTL call
|
||||
* @arg2 Argument 2 to requested IOCTL call
|
||||
* @arg3 Argument 3 to requested IOCTL call
|
||||
* @arg4 Argument 4 to requested IOCTL call
|
||||
* @data Returned output data
|
||||
*
|
||||
* This function returns requested data.
|
||||
*
|
||||
* @return Returns status, either success or error+reason
|
||||
*/
|
||||
enum pm_ret_status pm_query_data(enum pm_query_id qid,
|
||||
unsigned int arg1,
|
||||
unsigned int arg2,
|
||||
unsigned int arg3,
|
||||
unsigned int *data)
|
||||
{
|
||||
enum pm_ret_status ret;
|
||||
|
||||
switch (qid) {
|
||||
case PM_QID_CLOCK_GET_NAME:
|
||||
ret = pm_clock_get_name(arg1, (char *)data);
|
||||
break;
|
||||
case PM_QID_CLOCK_GET_TOPOLOGY:
|
||||
ret = pm_clock_get_topology(arg1, arg2, &data[1]);
|
||||
data[0] = (unsigned int)ret;
|
||||
break;
|
||||
case PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS:
|
||||
ret = pm_clock_get_fixedfactor_params(arg1, &data[1], &data[2]);
|
||||
data[0] = (unsigned int)ret;
|
||||
break;
|
||||
case PM_QID_CLOCK_GET_PARENTS:
|
||||
ret = pm_clock_get_parents(arg1, arg2, &data[1]);
|
||||
data[0] = (unsigned int)ret;
|
||||
break;
|
||||
case PM_QID_CLOCK_GET_ATTRIBUTES:
|
||||
ret = pm_clock_get_attributes(arg1, &data[1]);
|
||||
data[0] = (unsigned int)ret;
|
||||
break;
|
||||
case PM_QID_PINCTRL_GET_NUM_PINS:
|
||||
ret = pm_pinctrl_get_num_pins(&data[1]);
|
||||
data[0] = (unsigned int)ret;
|
||||
break;
|
||||
case PM_QID_PINCTRL_GET_NUM_FUNCTIONS:
|
||||
ret = pm_pinctrl_get_num_functions(&data[1]);
|
||||
data[0] = (unsigned int)ret;
|
||||
break;
|
||||
case PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS:
|
||||
ret = pm_pinctrl_get_num_function_groups(arg1, &data[1]);
|
||||
data[0] = (unsigned int)ret;
|
||||
break;
|
||||
case PM_QID_PINCTRL_GET_FUNCTION_NAME:
|
||||
ret = pm_pinctrl_get_function_name(arg1, (char *)data);
|
||||
break;
|
||||
case PM_QID_PINCTRL_GET_FUNCTION_GROUPS:
|
||||
ret = pm_pinctrl_get_function_groups(arg1, arg2,
|
||||
(uint16_t *)&data[1]);
|
||||
data[0] = (unsigned int)ret;
|
||||
break;
|
||||
case PM_QID_PINCTRL_GET_PIN_GROUPS:
|
||||
ret = pm_pinctrl_get_pin_groups(arg1, arg2,
|
||||
(uint16_t *)&data[1]);
|
||||
data[0] = (unsigned int)ret;
|
||||
break;
|
||||
default:
|
||||
ret = PM_RET_ERROR_ARGS;
|
||||
WARN("Unimplemented query service call: 0x%x\n", qid);
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -10,6 +10,21 @@
|
|||
#include <stdint.h>
|
||||
#include "pm_defs.h"
|
||||
|
||||
enum pm_query_id {
|
||||
PM_QID_INVALID,
|
||||
PM_QID_CLOCK_GET_NAME,
|
||||
PM_QID_CLOCK_GET_TOPOLOGY,
|
||||
PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
|
||||
PM_QID_CLOCK_GET_PARENTS,
|
||||
PM_QID_CLOCK_GET_ATTRIBUTES,
|
||||
PM_QID_PINCTRL_GET_NUM_PINS,
|
||||
PM_QID_PINCTRL_GET_NUM_FUNCTIONS,
|
||||
PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
|
||||
PM_QID_PINCTRL_GET_FUNCTION_NAME,
|
||||
PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
|
||||
PM_QID_PINCTRL_GET_PIN_GROUPS,
|
||||
};
|
||||
|
||||
/**********************************************************
|
||||
* System-level API function declarations
|
||||
**********************************************************/
|
||||
|
|
@ -93,5 +108,42 @@ enum pm_ret_status pm_fpga_get_status(unsigned int *value);
|
|||
|
||||
enum pm_ret_status pm_get_chipid(uint32_t *value);
|
||||
void pm_get_callbackdata(uint32_t *data, size_t count);
|
||||
|
||||
enum pm_ret_status pm_pinctrl_request(unsigned int pin);
|
||||
enum pm_ret_status pm_pinctrl_release(unsigned int pin);
|
||||
enum pm_ret_status pm_pinctrl_get_function(unsigned int pin,
|
||||
enum pm_node_id *nid);
|
||||
enum pm_ret_status pm_pinctrl_set_function(unsigned int pin,
|
||||
enum pm_node_id nid);
|
||||
enum pm_ret_status pm_pinctrl_get_config(unsigned int pin,
|
||||
unsigned int param,
|
||||
unsigned int *value);
|
||||
enum pm_ret_status pm_pinctrl_set_config(unsigned int pin,
|
||||
unsigned int param,
|
||||
unsigned int value);
|
||||
enum pm_ret_status pm_ioctl(enum pm_node_id nid,
|
||||
unsigned int ioctl_id,
|
||||
unsigned int arg1,
|
||||
unsigned int arg2,
|
||||
unsigned int *value);
|
||||
enum pm_ret_status pm_clock_enable(unsigned int clock_id);
|
||||
enum pm_ret_status pm_clock_disable(unsigned int clock_id);
|
||||
enum pm_ret_status pm_clock_getstate(unsigned int clock_id,
|
||||
unsigned int *state);
|
||||
enum pm_ret_status pm_clock_setdivider(unsigned int clock_id,
|
||||
unsigned int divider);
|
||||
enum pm_ret_status pm_clock_getdivider(unsigned int clock_id,
|
||||
unsigned int *divider);
|
||||
enum pm_ret_status pm_clock_setrate(unsigned int clock_id,
|
||||
uint64_t rate);
|
||||
enum pm_ret_status pm_clock_getrate(unsigned int clock_id,
|
||||
uint64_t *rate);
|
||||
enum pm_ret_status pm_clock_setparent(unsigned int clock_id,
|
||||
unsigned int parent_id);
|
||||
enum pm_ret_status pm_clock_getparent(unsigned int clock_id,
|
||||
unsigned int *parent_id);
|
||||
enum pm_ret_status pm_query_data(enum pm_query_id qid,
|
||||
unsigned int arg1,
|
||||
unsigned int arg2,
|
||||
unsigned int arg3,
|
||||
unsigned int *data);
|
||||
#endif /* _PM_API_SYS_H_ */
|
||||
|
|
|
|||
|
|
@ -19,6 +19,11 @@
|
|||
#define PAYLOAD_ARG_CNT 6U
|
||||
#define PAYLOAD_ARG_SIZE 4U /* size in bytes */
|
||||
|
||||
#define ZYNQMP_TZ_VERSION_MAJOR 1
|
||||
#define ZYNQMP_TZ_VERSION_MINOR 0
|
||||
#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
|
||||
ZYNQMP_TZ_VERSION_MINOR)
|
||||
|
||||
/**
|
||||
* pm_ipi - struct for capturing IPI-channel specific info
|
||||
* @apu_ipi_id APU IPI agent ID
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -17,8 +17,8 @@
|
|||
* Version number is a 32bit value, like:
|
||||
* (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR
|
||||
*/
|
||||
#define PM_VERSION_MAJOR 0
|
||||
#define PM_VERSION_MINOR 2
|
||||
#define PM_VERSION_MAJOR 1
|
||||
#define PM_VERSION_MINOR 0
|
||||
|
||||
#define PM_VERSION ((PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR)
|
||||
|
||||
|
|
@ -66,6 +66,28 @@ enum pm_api_id {
|
|||
PM_FPGA_LOAD,
|
||||
PM_FPGA_GET_STATUS,
|
||||
PM_GET_CHIPID,
|
||||
PM_SECURE_RSA_AES,
|
||||
PM_SECURE_SHA,
|
||||
PM_SECURE_RSA,
|
||||
PM_PINCTRL_REQUEST,
|
||||
PM_PINCTRL_RELEASE,
|
||||
PM_PINCTRL_GET_FUNCTION,
|
||||
PM_PINCTRL_SET_FUNCTION,
|
||||
PM_PINCTRL_CONFIG_PARAM_GET,
|
||||
PM_PINCTRL_CONFIG_PARAM_SET,
|
||||
PM_IOCTL,
|
||||
/* API to query information from firmware */
|
||||
PM_QUERY_DATA,
|
||||
/* Clock control API functions */
|
||||
PM_CLOCK_ENABLE,
|
||||
PM_CLOCK_DISABLE,
|
||||
PM_CLOCK_GETSTATE,
|
||||
PM_CLOCK_SETDIVIDER,
|
||||
PM_CLOCK_GETDIVIDER,
|
||||
PM_CLOCK_SETRATE,
|
||||
PM_CLOCK_GETRATE,
|
||||
PM_CLOCK_SETPARENT,
|
||||
PM_CLOCK_GETPARENT,
|
||||
PM_API_MAX
|
||||
};
|
||||
|
||||
|
|
@ -79,7 +101,7 @@ enum pm_node_id {
|
|||
NODE_RPU,
|
||||
NODE_RPU_0,
|
||||
NODE_RPU_1,
|
||||
NODE_PL,
|
||||
NODE_PLD,
|
||||
NODE_FPD,
|
||||
NODE_OCM_BANK_0,
|
||||
NODE_OCM_BANK_1,
|
||||
|
|
@ -132,7 +154,23 @@ enum pm_node_id {
|
|||
NODE_PCIE,
|
||||
NODE_PCAP,
|
||||
NODE_RTC,
|
||||
NODE_MAX
|
||||
NODE_LPD,
|
||||
NODE_VCU,
|
||||
NODE_IPI_RPU_1,
|
||||
NODE_IPI_PL_0,
|
||||
NODE_IPI_PL_1,
|
||||
NODE_IPI_PL_2,
|
||||
NODE_IPI_PL_3,
|
||||
NODE_PL,
|
||||
NODE_GEM_TSU,
|
||||
NODE_SWDT_0,
|
||||
NODE_SWDT_1,
|
||||
NODE_CSU,
|
||||
NODE_PJTAG,
|
||||
NODE_TRACE,
|
||||
NODE_TESTSCAN,
|
||||
NODE_PMU,
|
||||
NODE_MAX,
|
||||
};
|
||||
|
||||
enum pm_request_ack {
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -19,6 +19,7 @@
|
|||
#include "pm_ipi.h"
|
||||
|
||||
#define PM_GET_CALLBACK_DATA 0xa01
|
||||
#define PM_GET_TRUSTZONE_VERSION 0xa03
|
||||
|
||||
/* 0 - UP, !0 - DOWN */
|
||||
static int32_t pm_down = !0;
|
||||
|
|
@ -248,6 +249,118 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
|
|||
(uint64_t)result[2] | ((uint64_t)result[3] << 32));
|
||||
}
|
||||
|
||||
case PM_PINCTRL_REQUEST:
|
||||
ret = pm_pinctrl_request(pm_arg[0]);
|
||||
SMC_RET1(handle, (uint64_t)ret);
|
||||
|
||||
case PM_PINCTRL_RELEASE:
|
||||
ret = pm_pinctrl_release(pm_arg[0]);
|
||||
SMC_RET1(handle, (uint64_t)ret);
|
||||
|
||||
case PM_PINCTRL_GET_FUNCTION:
|
||||
{
|
||||
uint32_t value = 0;
|
||||
|
||||
ret = pm_pinctrl_get_function(pm_arg[0], &value);
|
||||
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
|
||||
}
|
||||
|
||||
case PM_PINCTRL_SET_FUNCTION:
|
||||
ret = pm_pinctrl_set_function(pm_arg[0], pm_arg[1]);
|
||||
SMC_RET1(handle, (uint64_t)ret);
|
||||
|
||||
case PM_PINCTRL_CONFIG_PARAM_GET:
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
ret = pm_pinctrl_get_config(pm_arg[0], pm_arg[1], &value);
|
||||
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
|
||||
}
|
||||
|
||||
case PM_PINCTRL_CONFIG_PARAM_SET:
|
||||
ret = pm_pinctrl_set_config(pm_arg[0], pm_arg[1], pm_arg[2]);
|
||||
SMC_RET1(handle, (uint64_t)ret);
|
||||
|
||||
case PM_IOCTL:
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
ret = pm_ioctl(pm_arg[0], pm_arg[1], pm_arg[2],
|
||||
pm_arg[3], &value);
|
||||
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
|
||||
}
|
||||
|
||||
case PM_QUERY_DATA:
|
||||
{
|
||||
uint32_t data[4] = { 0 };
|
||||
|
||||
ret = pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2],
|
||||
pm_arg[3], data);
|
||||
SMC_RET2(handle, (uint64_t)data[0] | ((uint64_t)data[1] << 32),
|
||||
(uint64_t)data[2] | ((uint64_t)data[3] << 32));
|
||||
}
|
||||
|
||||
case PM_CLOCK_ENABLE:
|
||||
ret = pm_clock_enable(pm_arg[0]);
|
||||
SMC_RET1(handle, (uint64_t)ret);
|
||||
|
||||
case PM_CLOCK_DISABLE:
|
||||
ret = pm_clock_disable(pm_arg[0]);
|
||||
SMC_RET1(handle, (uint64_t)ret);
|
||||
|
||||
case PM_CLOCK_GETSTATE:
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
ret = pm_clock_getstate(pm_arg[0], &value);
|
||||
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
|
||||
}
|
||||
|
||||
case PM_CLOCK_SETDIVIDER:
|
||||
ret = pm_clock_setdivider(pm_arg[0], pm_arg[1]);
|
||||
SMC_RET1(handle, (uint64_t)ret);
|
||||
|
||||
case PM_CLOCK_GETDIVIDER:
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
ret = pm_clock_getdivider(pm_arg[0], &value);
|
||||
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
|
||||
}
|
||||
|
||||
case PM_CLOCK_SETRATE:
|
||||
ret = pm_clock_setrate(pm_arg[0],
|
||||
((uint64_t)pm_arg[2]) << 32 | pm_arg[1]);
|
||||
|
||||
SMC_RET1(handle, (uint64_t)ret);
|
||||
|
||||
case PM_CLOCK_GETRATE:
|
||||
{
|
||||
uint64_t value;
|
||||
|
||||
ret = pm_clock_getrate(pm_arg[0], &value);
|
||||
SMC_RET2(handle, (uint64_t)ret |
|
||||
(((uint64_t)value & 0xFFFFFFFFU) << 32U),
|
||||
(value >> 32U) & 0xFFFFFFFFU);
|
||||
|
||||
}
|
||||
|
||||
case PM_CLOCK_SETPARENT:
|
||||
ret = pm_clock_setparent(pm_arg[0], pm_arg[1]);
|
||||
SMC_RET1(handle, (uint64_t)ret);
|
||||
|
||||
case PM_CLOCK_GETPARENT:
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
ret = pm_clock_getparent(pm_arg[0], &value);
|
||||
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
|
||||
}
|
||||
|
||||
case PM_GET_TRUSTZONE_VERSION:
|
||||
SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS |
|
||||
((uint64_t)ZYNQMP_TZ_VERSION << 32));
|
||||
|
||||
default:
|
||||
WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid);
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -27,33 +27,36 @@
|
|||
* ZYNQMP memory map related constants
|
||||
******************************************************************************/
|
||||
/* Aggregate of all devices in the first GB */
|
||||
#define DEVICE0_BASE 0xFF000000
|
||||
#define DEVICE0_SIZE 0x00E00000
|
||||
#define DEVICE1_BASE 0xF9000000
|
||||
#define DEVICE1_SIZE 0x00800000
|
||||
#define DEVICE0_BASE U(0xFF000000)
|
||||
#define DEVICE0_SIZE U(0x00E00000)
|
||||
#define DEVICE1_BASE U(0xF9000000)
|
||||
#define DEVICE1_SIZE U(0x00800000)
|
||||
|
||||
/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
|
||||
#define CRF_APB_BASE 0xFD1A0000
|
||||
#define CRF_APB_SIZE 0x00600000
|
||||
#define CRF_APB_BASE U(0xFD1A0000)
|
||||
#define CRF_APB_SIZE U(0x00600000)
|
||||
#define CRF_APB_CLK_BASE U(0xFD1A0020)
|
||||
|
||||
/* CRF registers and bitfields */
|
||||
#define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104)
|
||||
|
||||
#define CRF_APB_RST_FPD_APU_ACPU_RESET (1 << 0)
|
||||
#define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (1 << 10)
|
||||
#define CRF_APB_RST_FPD_APU_ACPU_RESET (U(1) << 0)
|
||||
#define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (U(1) << 10)
|
||||
|
||||
/* CRL registers and bitfields */
|
||||
#define CRL_APB_BASE 0xFF5E0000
|
||||
#define CRL_APB_RPLL_CTRL (CRL_APB_BASE + 0x30)
|
||||
#define CRL_APB_BASE U(0xFF5E0000)
|
||||
#define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200)
|
||||
#define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218)
|
||||
#define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C)
|
||||
#define CRL_APB_CLK_BASE U(0xFF5E0020)
|
||||
|
||||
#define CRL_APB_RPLL_CTRL_BYPASS (1 << 3)
|
||||
#define CRL_APB_RPU_AMBA_RESET (U(1) << 2)
|
||||
#define CRL_APB_RPLL_CTRL_BYPASS (U(1) << 3)
|
||||
|
||||
#define CRL_APB_RESET_CTRL_SOFT_RESET (1 << 4)
|
||||
#define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4)
|
||||
|
||||
#define CRL_APB_BOOT_MODE_MASK (0xf << 0)
|
||||
#define ZYNQMP_BOOTMODE_JTAG 0
|
||||
#define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0)
|
||||
#define ZYNQMP_BOOTMODE_JTAG U(0)
|
||||
|
||||
/* system counter registers and bitfields */
|
||||
#define IOU_SCNTRS_BASE 0xFF260000
|
||||
|
|
@ -174,4 +177,138 @@
|
|||
#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
|
||||
#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
|
||||
|
||||
#define IOU_SLCR_BASEADDR U(0xFF180000)
|
||||
|
||||
#define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000)
|
||||
#define ZYNQMP_RPU0_CFG U(0xFF9A0100)
|
||||
#define ZYNQMP_RPU1_CFG U(0xFF9A0200)
|
||||
#define ZYNQMP_SLSPLIT_MASK U(0x08)
|
||||
#define ZYNQMP_TCM_COMB_MASK U(0x40)
|
||||
#define ZYNQMP_SLCLAMP_MASK U(0x10)
|
||||
#define ZYNQMP_VINITHI_MASK U(0x04)
|
||||
|
||||
/* Tap delay bypass */
|
||||
#define IOU_TAPDLY_BYPASS U(0XFF180390)
|
||||
#define TAP_DELAY_MASK U(0x7)
|
||||
|
||||
/* SGMII mode */
|
||||
#define IOU_GEM_CTRL U(0xFF180360)
|
||||
#define IOU_GEM_CLK_CTRL U(0xFF180308)
|
||||
#define SGMII_SD_MASK U(0x3)
|
||||
#define SGMII_SD_OFFSET U(2)
|
||||
#define SGMII_PCS_SD_0 U(0x0)
|
||||
#define SGMII_PCS_SD_1 U(0x1)
|
||||
#define SGMII_PCS_SD_PHY U(0x2)
|
||||
#define GEM_SGMII_MASK U(0x4)
|
||||
#define GEM_CLK_CTRL_MASK U(0xF)
|
||||
#define GEM_CLK_CTRL_OFFSET U(5)
|
||||
#define GEM_RX_SRC_SEL_GTR U(0x1)
|
||||
#define GEM_SGMII_MODE U(0x4)
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/* SD DLL reset */
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#define ZYNQMP_SD_DLL_CTRL U(0xFF180358)
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#define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004)
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#define ZYNQMP_SD0_DLL_RST U(0x00000004)
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#define ZYNQMP_SD1_DLL_RST_MASK U(0x00040000)
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#define ZYNQMP_SD1_DLL_RST U(0x00040000)
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/* SD tap delay */
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#define ZYNQMP_SD_DLL_CTRL U(0xFF180358)
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#define ZYNQMP_SD_ITAP_DLY U(0xFF180314)
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#define ZYNQMP_SD_OTAP_DLY U(0xFF180318)
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#define ZYNQMP_SD_TAP_OFFSET U(16)
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#define ZYNQMP_SD_ITAPCHGWIN_MASK U(0x200)
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#define ZYNQMP_SD_ITAPCHGWIN U(0x200)
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#define ZYNQMP_SD_ITAPDLYENA_MASK U(0x100)
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#define ZYNQMP_SD_ITAPDLYENA U(0x100)
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#define ZYNQMP_SD_ITAPDLYSEL_MASK U(0xFF)
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#define ZYNQMP_SD_OTAPDLYSEL_MASK U(0x3F)
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#define ZYNQMP_SD_OTAPDLYENA_MASK U(0x40)
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#define ZYNQMP_SD_OTAPDLYENA U(0x40)
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||||
/* Clock control registers */
|
||||
/* Full power domain clocks */
|
||||
#define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00)
|
||||
#define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c)
|
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#define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18)
|
||||
#define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24)
|
||||
#define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28)
|
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#define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c)
|
||||
#define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30)
|
||||
/* Peripheral clocks */
|
||||
#define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40)
|
||||
#define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44)
|
||||
#define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48)
|
||||
#define CRF_APB_DP_VIDEO_REF_CTRL (CRF_APB_CLK_BASE + 0x50)
|
||||
#define CRF_APB_DP_AUDIO_REF_CTRL (CRF_APB_CLK_BASE + 0x54)
|
||||
#define CRF_APB_DP_STC_REF_CTRL (CRF_APB_CLK_BASE + 0x5c)
|
||||
#define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60)
|
||||
#define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64)
|
||||
#define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80)
|
||||
#define CRF_APB_PCIE_REF_CTRL (CRF_APB_CLK_BASE + 0x94)
|
||||
#define CRF_APB_GDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x98)
|
||||
#define CRF_APB_DPDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x9c)
|
||||
#define CRF_APB_TOPSW_MAIN_CTRL (CRF_APB_CLK_BASE + 0xa0)
|
||||
#define CRF_APB_TOPSW_LSBUS_CTRL (CRF_APB_CLK_BASE + 0xa4)
|
||||
#define CRF_APB_GTGREF0_REF_CTRL (CRF_APB_CLK_BASE + 0xa8)
|
||||
#define CRF_APB_DBG_TSTMP_CTRL (CRF_APB_CLK_BASE + 0xd8)
|
||||
|
||||
/* Low power domain clocks */
|
||||
#define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00)
|
||||
#define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10)
|
||||
#define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20)
|
||||
#define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24)
|
||||
#define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28)
|
||||
/* Peripheral clocks */
|
||||
#define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c)
|
||||
#define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30)
|
||||
#define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34)
|
||||
#define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38)
|
||||
#define CRL_APB_GEM3_REF_CTRL (CRL_APB_CLK_BASE + 0x3c)
|
||||
#define CRL_APB_USB0_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x40)
|
||||
#define CRL_APB_USB1_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x44)
|
||||
#define CRL_APB_QSPI_REF_CTRL (CRL_APB_CLK_BASE + 0x48)
|
||||
#define CRL_APB_SDIO0_REF_CTRL (CRL_APB_CLK_BASE + 0x4c)
|
||||
#define CRL_APB_SDIO1_REF_CTRL (CRL_APB_CLK_BASE + 0x50)
|
||||
#define CRL_APB_UART0_REF_CTRL (CRL_APB_CLK_BASE + 0x54)
|
||||
#define CRL_APB_UART1_REF_CTRL (CRL_APB_CLK_BASE + 0x58)
|
||||
#define CRL_APB_SPI0_REF_CTRL (CRL_APB_CLK_BASE + 0x5c)
|
||||
#define CRL_APB_SPI1_REF_CTRL (CRL_APB_CLK_BASE + 0x60)
|
||||
#define CRL_APB_CAN0_REF_CTRL (CRL_APB_CLK_BASE + 0x64)
|
||||
#define CRL_APB_CAN1_REF_CTRL (CRL_APB_CLK_BASE + 0x68)
|
||||
#define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70)
|
||||
#define CRL_APB_IOU_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x7c)
|
||||
#define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80)
|
||||
#define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84)
|
||||
#define CRL_APB_LPD_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x88)
|
||||
#define CRL_APB_LPD_LSBUS_CTRL (CRL_APB_CLK_BASE + 0x8c)
|
||||
#define CRL_APB_DBG_LPD_CTRL (CRL_APB_CLK_BASE + 0x90)
|
||||
#define CRL_APB_NAND_REF_CTRL (CRL_APB_CLK_BASE + 0x94)
|
||||
#define CRL_APB_ADMA_REF_CTRL (CRL_APB_CLK_BASE + 0x98)
|
||||
#define CRL_APB_PL0_REF_CTRL (CRL_APB_CLK_BASE + 0xa0)
|
||||
#define CRL_APB_PL1_REF_CTRL (CRL_APB_CLK_BASE + 0xa4)
|
||||
#define CRL_APB_PL2_REF_CTRL (CRL_APB_CLK_BASE + 0xa8)
|
||||
#define CRL_APB_PL3_REF_CTRL (CRL_APB_CLK_BASE + 0xac)
|
||||
#define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4)
|
||||
#define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc)
|
||||
#define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4)
|
||||
#define CRL_APB_PL3_THR_CNT (CRL_APB_CLK_BASE + 0xdc)
|
||||
#define CRL_APB_GEM_TSU_REF_CTRL (CRL_APB_CLK_BASE + 0xe0)
|
||||
#define CRL_APB_DLL_REF_CTRL (CRL_APB_CLK_BASE + 0xe4)
|
||||
#define CRL_APB_AMS_REF_CTRL (CRL_APB_CLK_BASE + 0xe8)
|
||||
#define CRL_APB_I2C0_REF_CTRL (CRL_APB_CLK_BASE + 0x100)
|
||||
#define CRL_APB_I2C1_REF_CTRL (CRL_APB_CLK_BASE + 0x104)
|
||||
#define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108)
|
||||
#define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308)
|
||||
#define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304)
|
||||
#define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300)
|
||||
|
||||
/* Global general storage register base address */
|
||||
#define GGS_BASEADDR (0xFFD80030U)
|
||||
#define GGS_NUM_REGS U(4)
|
||||
|
||||
/* Persistent global general storage register base address */
|
||||
#define PGGS_BASEADDR (0xFFD80050U)
|
||||
#define PGGS_NUM_REGS U(4)
|
||||
|
||||
#endif /* __ZYNQMP_DEF_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue