feat: adding the diphda platform
This commit enables trusted-firmware-a with Trusted Board Boot support for the Diphda 64-bit platform. Diphda uses a FIP image located in the flash. The FIP contains the following components: - BL2 - BL31 - BL32 - BL32 SPMC manifest - BL33 - The TBB certificates The board boot relies on CoT (chain of trust). The trusted-firmware-a BL2 is extracted from the FIP and verified by the Secure Enclave processor. BL2 verification relies on the signature area at the beginning of the BL2 image. This area is needed by the SecureEnclave bootloader. Then, the application processor is released from reset and starts by executing BL2. BL2 performs the actions described in the trusted-firmware-a TBB design document. Signed-off-by: Rui Miguel Silva <rui.silva@arm.com> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Change-Id: Iddb1cb9c2a0324a9635e23821c210ac81dfc305d
This commit is contained in:
Abdellatif El Khlifi
parent
52eb322919
commit
bf3ce99371
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@ -399,6 +399,7 @@ Arm Rich IoT Platform ports
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:|G|: `vishnu-banavath`_
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:|F|: plat/arm/board/corstone700
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:|F|: plat/arm/board/a5ds
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:|F|: plat/arm/board/diphda
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Arm Reference Design platform ports
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -0,0 +1,61 @@
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Diphda Platform
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==========================
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Some of the features of the Diphda platform referenced in TF-A include:
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- Cortex-A35 application processor (64-bit mode)
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- Secure Enclave
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- GIC-400
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- Trusted Board Boot
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Boot Sequence
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-------------
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The board boot relies on CoT (chain of trust). The trusted-firmware-a
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BL2 is extracted from the FIP and verified by the Secure Enclave
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processor. BL2 verification relies on the signature area at the
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beginning of the BL2 image. This area is needed by the SecureEnclave
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bootloader.
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Then, the application processor is released from reset and starts by
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executing BL2.
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BL2 performs the actions described in the trusted-firmware-a TBB design
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document.
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Build Procedure (TF-A only)
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~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Obtain AArch64 ELF bare-metal target `toolchain <https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads>`_.
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Set the CROSS_COMPILE environment variable to point to the toolchain folder.
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- Build TF-A:
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.. code:: shell
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make LD=aarch64-none-elf-ld \
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CC=aarch64-none-elf-gcc \
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V=1 \
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BUILD_BASE=<path to the build folder> \
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PLAT=diphda \
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SPD=spmd \
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SPMD_SPM_AT_SEL2=0 \
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DEBUG=1 \
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MBEDTLS_DIR=mbedtls \
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OPENSSL_DIR=<path to openssl usr folder> \
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RUNTIME_SYSROOT=<path to the sysroot> \
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ARCH=aarch64 \
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TARGET_PLATFORM=<fpga or fvp> \
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ENABLE_PIE=1 \
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BL2_AT_EL3=1 \
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CREATE_KEYS=1 \
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GENERATE_COT=1 \
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TRUSTED_BOARD_BOOT=1 \
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COT=tbbr \
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ARM_ROTPK_LOCATION=devel_rsa \
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ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
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BL32=<path to optee binary> \
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BL33=<path to u-boot binary> \
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bl2
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*Copyright (c) 2021, Arm Limited. All rights reserved.*
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@ -12,6 +12,7 @@ Arm Development Platforms
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arm_fpga/index
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arm-build-options
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morello/index
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diphda/index
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This chapter holds documentation related to Arm's development platforms,
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including both software models (FVPs) and hardware development boards
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@ -19,4 +20,4 @@ such as Juno.
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--------------
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*Copyright (c) 2019, Arm Limited. All rights reserved.*
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*Copyright (c) 2021, Arm Limited. All rights reserved.*
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@ -1,10 +1,17 @@
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/*
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* Copyright (c) 2020, ARM Limited. All rights reserved.
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* Copyright (c) 2021, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* diphda platform provides custom values for the macros defined in
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* arm_def.h , so only platform_def.h needs to be included
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*/
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#if !defined(TARGET_PLATFORM_FVP) && !defined(TARGET_PLATFORM_FPGA)
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#include "plat/arm/common/arm_def.h"
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#else
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#include <platform_def.h>
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#endif
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.global arm_rotpk_header
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.global arm_rotpk_header_end
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@ -0,0 +1,86 @@
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/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/desc_image_load.h>
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#include <platform_def.h>
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/*******************************************************************************
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* Following descriptor provides BL image/ep information that gets used
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* by BL2 to load the images and also subset of this information is
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* passed to next BL image. The image loading sequence is managed by
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* populating the images in required loading order. The image execution
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* sequence is managed by populating the `next_handoff_image_id` with
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* the next executable image id.
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******************************************************************************/
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static bl_mem_params_node_t bl2_mem_params_descs[] = {
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/* Fill BL31 related information */
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{
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.image_id = BL31_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.pc = BL31_BASE,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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.ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
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.image_info.image_base = BL31_BASE,
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.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
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.next_handoff_image_id = BL32_IMAGE_ID,
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},
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/* Fill BL32 related information */
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{
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.image_id = BL32_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
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.ep_info.pc = BL32_BASE,
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.ep_info.args.arg0 = DIPHDA_TOS_FW_CONFIG_BASE,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = BL32_BASE,
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.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
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.next_handoff_image_id = BL33_IMAGE_ID,
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},
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/* Fill TOS_FW_CONFIG related information */
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{
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.image_id = TOS_FW_CONFIG_ID,
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.image_info.image_base = DIPHDA_TOS_FW_CONFIG_BASE,
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.image_info.image_max_size = DIPHDA_TOS_FW_CONFIG_LIMIT - \
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DIPHDA_TOS_FW_CONFIG_BASE,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
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VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
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VERSION_2, image_info_t, 0),
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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/* Fill BL33 related information */
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{
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.image_id = BL33_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
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.ep_info.pc = PLAT_ARM_NS_IMAGE_BASE,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = PLAT_ARM_NS_IMAGE_BASE,
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.image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE
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- PLAT_ARM_NS_IMAGE_BASE,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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};
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REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
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/*
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* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/arm/common/plat_arm.h>
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/*
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* diphda error handler
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*/
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void __dead2 plat_arm_error_handler(int err)
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{
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while (1) {
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wfi();
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}
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}
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/*
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* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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.globl plat_secondary_cold_boot_setup
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.globl plat_get_my_entrypoint
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.globl plat_is_my_cpu_primary
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.globl plat_arm_calc_core_pos
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/* --------------------------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* For AArch32, cold-booting secondary CPUs is not yet
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* implemented and they panic.
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* --------------------------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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cb_panic:
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b cb_panic
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endfunc plat_secondary_cold_boot_setup
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/* ---------------------------------------------------------------------
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* unsigned long plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between a cold and warm
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* boot. On diphda, this information can be queried from the power
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* controller. The Power Control SYS Status Register (PSYSR) indicates
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* the wake-up reason for the CPU.
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*
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* For a cold boot, return 0.
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* For a warm boot, Not yet supported.
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*
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* TODO: PSYSR is a common register and should be
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* accessed using locks. Since it is not possible
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* to use locks immediately after a cold reset
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* we are relying on the fact that after a cold
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* reset all cpus will read the same WK field
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* ---------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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/* TODO support warm boot */
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/* Cold reset */
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mov x0, #0
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ret
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current CPU is the primary
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* CPU.
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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mov_imm x1, MPIDR_AFFINITY_MASK
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and x0, x0, x1
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cmp x0, #DIPHDA_PRIMARY_CPU
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cset w0, eq
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ret
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endfunc plat_is_my_cpu_primary
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/*
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* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/bl_common.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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/*
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* Table of regions to map using the MMU.
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* Replace or extend the below regions as required
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*/
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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ARM_MAP_NS_SHARED_RAM,
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ARM_MAP_NS_DRAM1,
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DIPHDA_MAP_DEVICE,
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DIPHDA_EXTERNAL_FLASH,
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{0}
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};
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/* diphda only has one always-on power domain and there
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* is no power control present
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*/
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void __init plat_arm_pwrc_setup(void)
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{
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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/* Returning the Generic Timer Frequency */
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return SYS_COUNTER_FREQ_IN_TICKS;
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}
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/*
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* Helper function to initialize ARM interconnect driver.
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*/
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void plat_arm_interconnect_init(void)
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{
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}
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/*
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* Helper function to place current master into coherency
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*/
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void plat_arm_interconnect_enter_coherency(void)
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{
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}
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/*
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* Helper function to remove current master from coherency
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*/
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void plat_arm_interconnect_exit_coherency(void)
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{
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}
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/*
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* This function is invoked during Mbed TLS library initialisation to get a heap
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* The function simply returns the default allocated heap.
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*/
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#if TRUSTED_BOARD_BOOT
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int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
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{
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assert(heap_addr != NULL);
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assert(heap_size != NULL);
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return arm_get_mbedtls_heap(heap_addr, heap_size);
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}
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#endif
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@ -0,0 +1,22 @@
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/*
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* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/psci/psci.h>
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#include <plat/arm/common/plat_arm.h>
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/*******************************************************************************
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* Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
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* platform layer will take care of registering the handlers with PSCI.
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******************************************************************************/
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plat_psci_ops_t plat_arm_psci_pm_ops = {
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/* dummy struct */
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.validate_ns_entrypoint = NULL
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};
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const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
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{
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return ops;
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}
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|
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@ -0,0 +1,16 @@
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/*
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* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
|
||||
*
|
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* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
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/*
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* We assume that all security programming is done by the primary core.
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*/
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void plat_arm_security_setup(void)
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{
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/*
|
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* If the platform had additional peripheral specific security
|
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* configurations, those would be configured here.
|
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*/
|
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}
|
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|
|
@ -0,0 +1,35 @@
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/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
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#include <arch_helpers.h>
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#include <plat/common/platform.h>
|
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|
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static uint32_t plat_generate_random_number(void)
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{
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uintptr_t return_addr = (uintptr_t)__builtin_return_address(0U);
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uintptr_t frame_addr = (uintptr_t)__builtin_frame_address(0U);
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uint64_t cntpct = read_cntpct_el0();
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/* Generate 32-bit pattern: saving the 2 least significant bytes
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* in random_lo and random_hi
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*/
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uint16_t random_lo = (uint16_t)(
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(((uint64_t)return_addr) << 13) ^ frame_addr ^ cntpct
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);
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uint16_t random_hi = (uint16_t)(
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(((uint64_t)frame_addr) << 15) ^ return_addr ^ cntpct
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);
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||||
return (((uint32_t)random_hi) << 16) | random_lo;
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}
|
||||
|
||||
u_register_t plat_get_stack_protector_canary(void)
|
||||
{
|
||||
return plat_generate_random_number(); /* a 32-bit pattern returned */
|
||||
}
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <plat/arm/common/plat_arm.h>
|
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#include <plat/common/platform.h>
|
||||
|
||||
/* The diphda power domain tree descriptor */
|
||||
static unsigned char diphda_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT
|
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+ 2];
|
||||
/*******************************************************************************
|
||||
* This function dynamically constructs the topology according to
|
||||
* CLUSTER_COUNT and returns it.
|
||||
******************************************************************************/
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* The highest level is the system level. The next level is constituted
|
||||
* by clusters and then cores in clusters.
|
||||
*/
|
||||
diphda_power_domain_tree_desc[0] = 1;
|
||||
diphda_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT;
|
||||
|
||||
for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++)
|
||||
diphda_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT;
|
||||
|
||||
return diphda_power_domain_tree_desc;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* This function implements a part of the critical interface between the PSCI
|
||||
* generic layer and the platform that allows the former to query the platform
|
||||
* to convert an MPIDR to a unique linear index. An error code (-1) is
|
||||
* returned in case the MPIDR is invalid.
|
||||
*****************************************************************************/
|
||||
int plat_core_pos_by_mpidr(u_register_t mpidr)
|
||||
{
|
||||
return plat_arm_calc_core_pos(mpidr);
|
||||
}
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
|
||||
/*
|
||||
* Return the ROTPK hash in the following ASN.1 structure in DER format:
|
||||
*
|
||||
* AlgorithmIdentifier ::= SEQUENCE {
|
||||
* algorithm OBJECT IDENTIFIER,
|
||||
* parameters ANY DEFINED BY algorithm OPTIONAL
|
||||
* }
|
||||
*
|
||||
* DigestInfo ::= SEQUENCE {
|
||||
* digestAlgorithm AlgorithmIdentifier,
|
||||
* digest OCTET STRING
|
||||
* }
|
||||
*
|
||||
* The function returns 0 on success. Any other value is treated as error by the
|
||||
* Trusted Board Boot. The function also reports extra information related
|
||||
* to the ROTPK in the flags parameter: ROTPK_IS_HASH, ROTPK_NOT_DEPLOYED.
|
||||
*
|
||||
* Refer to the TF-A porting-guide document for more details.
|
||||
*/
|
||||
int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
|
||||
unsigned int *flags)
|
||||
{
|
||||
return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
|
||||
}
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
compatible = "arm,ffa-core-manifest-1.0";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/*
|
||||
* BL32 image details needed by SPMC
|
||||
*
|
||||
* Note:
|
||||
* binary_size: size of BL32 + TOS_FW_CONFIG
|
||||
*/
|
||||
|
||||
attribute {
|
||||
spmc_id = <0x8000>;
|
||||
maj_ver = <0x1>;
|
||||
min_ver = <0x0>;
|
||||
exec_state = <0x0>;
|
||||
load_address = <0x0 0x2002000>;
|
||||
entrypoint = <0x0 0x2002000>;
|
||||
binary_size = <0xae000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -0,0 +1,416 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
||||
|
||||
#include <common/tbbr/tbbr_img_def.h>
|
||||
#include <lib/utils_def.h>
|
||||
#include <lib/xlat_tables/xlat_tables_defs.h>
|
||||
#include <plat/arm/board/common/v2m_def.h>
|
||||
#include <plat/arm/common/arm_spm_def.h>
|
||||
#include <plat/arm/common/smccc_def.h>
|
||||
#include <plat/common/common_def.h>
|
||||
#include <plat/arm/soc/common/soc_css_def.h>
|
||||
|
||||
#define ARM_ROTPK_HEADER_LEN 19
|
||||
#define ARM_ROTPK_HASH_LEN 32
|
||||
|
||||
/* Special value used to verify platform parameters from BL2 to BL31 */
|
||||
#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
|
||||
|
||||
/* PL011 UART related constants */
|
||||
#ifdef V2M_IOFPGA_UART0_CLK_IN_HZ
|
||||
#undef V2M_IOFPGA_UART0_CLK_IN_HZ
|
||||
#endif
|
||||
|
||||
#ifdef V2M_IOFPGA_UART1_CLK_IN_HZ
|
||||
#undef V2M_IOFPGA_UART1_CLK_IN_HZ
|
||||
#endif
|
||||
|
||||
#define V2M_IOFPGA_UART0_CLK_IN_HZ 50000000
|
||||
#define V2M_IOFPGA_UART1_CLK_IN_HZ 50000000
|
||||
|
||||
/* Core/Cluster/Thread counts for diphda */
|
||||
#define DIPHDA_CLUSTER_COUNT U(1)
|
||||
#define DIPHDA_MAX_CPUS_PER_CLUSTER U(4)
|
||||
#define DIPHDA_MAX_PE_PER_CPU U(1)
|
||||
#define DIPHDA_PRIMARY_CPU U(0)
|
||||
|
||||
#define PLAT_ARM_CLUSTER_COUNT DIPHDA_CLUSTER_COUNT
|
||||
|
||||
#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \
|
||||
DIPHDA_MAX_CPUS_PER_CLUSTER * \
|
||||
DIPHDA_MAX_PE_PER_CPU)
|
||||
|
||||
/* UART related constants */
|
||||
#define PLAT_ARM_BOOT_UART_BASE 0x1a510000
|
||||
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
|
||||
#define PLAT_ARM_RUN_UART_BASE 0x1a520000
|
||||
#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
|
||||
#define ARM_CONSOLE_BAUDRATE 115200
|
||||
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
|
||||
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
|
||||
|
||||
/* Memory related constants */
|
||||
|
||||
/* SRAM (CVM) memory layout
|
||||
*
|
||||
* <ARM_TRUSTED_SRAM_BASE>
|
||||
*
|
||||
* partition size: sizeof(meminfo_t) = 16 bytes
|
||||
*
|
||||
* content: memory info area used by the next BL
|
||||
*
|
||||
* <ARM_FW_CONFIG_BASE>
|
||||
*
|
||||
* partition size: 4080 bytes
|
||||
*
|
||||
* <ARM_BL2_MEM_DESC_BASE>
|
||||
*
|
||||
* partition size: 4 KB
|
||||
*
|
||||
* content:
|
||||
*
|
||||
* Area where BL2 copies the images descriptors
|
||||
*
|
||||
* <ARM_BL_RAM_BASE> = <BL32_BASE>
|
||||
*
|
||||
* partition size: 688 KB
|
||||
*
|
||||
* content:
|
||||
*
|
||||
* BL32 (optee-os)
|
||||
*
|
||||
* <DIPHDA_TOS_FW_CONFIG_BASE> = 0x20ae000
|
||||
*
|
||||
* partition size: 8 KB
|
||||
*
|
||||
* content:
|
||||
*
|
||||
* BL32 config (TOS_FW_CONFIG)
|
||||
*
|
||||
* <BL31_BASE>
|
||||
*
|
||||
* partition size: 140 KB
|
||||
*
|
||||
* content:
|
||||
*
|
||||
* BL31
|
||||
*
|
||||
* <BL2_SIGNATURE_BASE>
|
||||
*
|
||||
* partition size: 4 KB
|
||||
*
|
||||
* content:
|
||||
*
|
||||
* MCUBOOT data needed to verify TF-A BL2
|
||||
*
|
||||
* <BL2_BASE>
|
||||
*
|
||||
* partition size: 176 KB
|
||||
*
|
||||
* content:
|
||||
*
|
||||
* BL2
|
||||
*
|
||||
* <ARM_NS_SHARED_RAM_BASE> = <ARM_TRUSTED_SRAM_BASE> + 1 MB
|
||||
*
|
||||
* partition size: 3 MB
|
||||
*
|
||||
* content:
|
||||
*
|
||||
* BL33 (u-boot)
|
||||
*/
|
||||
|
||||
/* DDR memory */
|
||||
#define ARM_DRAM1_BASE UL(0x80000000)
|
||||
#define ARM_DRAM1_SIZE UL(0x80000000)
|
||||
#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
|
||||
ARM_DRAM1_SIZE - 1)
|
||||
|
||||
/* DRAM1 and DRAM2 are the same for diphda */
|
||||
#define ARM_DRAM2_BASE ARM_DRAM1_BASE
|
||||
#define ARM_DRAM2_SIZE ARM_DRAM1_SIZE
|
||||
#define ARM_DRAM2_END ARM_DRAM1_END
|
||||
|
||||
#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
|
||||
#define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE
|
||||
#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
|
||||
ARM_NS_DRAM1_SIZE - 1)
|
||||
|
||||
/* The first 8 KB of Trusted SRAM are used as shared memory */
|
||||
#define ARM_TRUSTED_SRAM_BASE UL(0x02000000)
|
||||
#define ARM_SHARED_RAM_SIZE UL(0x00002000) /* 8 KB */
|
||||
#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
|
||||
|
||||
/* The remaining Trusted SRAM is used to load the BL images */
|
||||
|
||||
#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00100000) /* 1 MB */
|
||||
|
||||
#define PLAT_ARM_MAX_BL2_SIZE UL(0x0002d000) /* 180 KB */
|
||||
|
||||
#define PLAT_ARM_MAX_BL31_SIZE UL(0x00023000) /* 140 KB */
|
||||
|
||||
#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
|
||||
ARM_SHARED_RAM_SIZE)
|
||||
#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
|
||||
ARM_SHARED_RAM_SIZE)
|
||||
|
||||
#define BL2_SIGNATURE_SIZE UL(0x00001000) /* 4 KB */
|
||||
#define BL2_SIGNATURE_BASE (BL2_LIMIT - \
|
||||
PLAT_ARM_MAX_BL2_SIZE)
|
||||
#define BL2_BASE (BL2_LIMIT - \
|
||||
PLAT_ARM_MAX_BL2_SIZE + \
|
||||
BL2_SIGNATURE_SIZE)
|
||||
#define BL2_LIMIT (ARM_BL_RAM_BASE + \
|
||||
ARM_BL_RAM_SIZE)
|
||||
|
||||
#define BL31_BASE (BL2_SIGNATURE_BASE - \
|
||||
PLAT_ARM_MAX_BL31_SIZE)
|
||||
#define BL31_LIMIT BL2_SIGNATURE_BASE
|
||||
|
||||
#define DIPHDA_TOS_FW_CONFIG_BASE (BL31_BASE - \
|
||||
DIPHDA_TOS_FW_CONFIG_SIZE)
|
||||
#define DIPHDA_TOS_FW_CONFIG_SIZE UL(0x00002000) /* 8 KB */
|
||||
#define DIPHDA_TOS_FW_CONFIG_LIMIT BL31_BASE
|
||||
|
||||
#define BL32_BASE ARM_BL_RAM_BASE
|
||||
#define PLAT_ARM_MAX_BL32_SIZE (DIPHDA_TOS_FW_CONFIG_BASE - \
|
||||
BL32_BASE) /* 688 KB */
|
||||
#define BL32_LIMIT (BL32_BASE + \
|
||||
PLAT_ARM_MAX_BL32_SIZE)
|
||||
|
||||
/* SPD_spmd settings */
|
||||
|
||||
#define PLAT_ARM_SPMC_BASE BL32_BASE
|
||||
#define PLAT_ARM_SPMC_SIZE PLAT_ARM_MAX_BL32_SIZE
|
||||
|
||||
/* NS memory */
|
||||
|
||||
/* The last 3 MB of the SRAM is allocated to the non secure area */
|
||||
#define ARM_NS_SHARED_RAM_BASE (ARM_TRUSTED_SRAM_BASE + \
|
||||
PLAT_ARM_TRUSTED_SRAM_SIZE)
|
||||
#define ARM_NS_SHARED_RAM_SIZE UL(0x00300000) /* 3 MB */
|
||||
|
||||
/* end of the definition of SRAM memory layout */
|
||||
|
||||
/* NOR Flash */
|
||||
|
||||
#define PLAT_ARM_FIP_BASE UL(0x08131000)
|
||||
#define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */
|
||||
|
||||
#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
|
||||
#define PLAT_ARM_NVM_SIZE UL(0x02000000) /* 32 MB */
|
||||
|
||||
#define PLAT_ARM_FLASH_IMAGE_BASE PLAT_ARM_FIP_BASE
|
||||
#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE PLAT_ARM_FIP_MAX_SIZE
|
||||
|
||||
/*
|
||||
* Some data must be aligned on the biggest cache line size in the platform.
|
||||
* This is known only to the platform as it might have a combination of
|
||||
* integrated and external caches.
|
||||
*/
|
||||
#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
|
||||
#define ARM_CACHE_WRITEBACK_SHIFT 6
|
||||
|
||||
/*
|
||||
* Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo.
|
||||
* FW_CONFIG is intended to host the device tree. Currently, This area is not
|
||||
* used because diphda platform doesn't use a device tree at TF-A level.
|
||||
*/
|
||||
#define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE \
|
||||
+ sizeof(meminfo_t))
|
||||
#define ARM_FW_CONFIG_LIMIT (ARM_SHARED_RAM_BASE \
|
||||
+ (ARM_SHARED_RAM_SIZE >> 1))
|
||||
|
||||
/*
|
||||
* Boot parameters passed from BL2 to BL31/BL32 are stored here
|
||||
*/
|
||||
#define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT
|
||||
#define ARM_BL2_MEM_DESC_LIMIT ARM_BL_RAM_BASE
|
||||
|
||||
/*
|
||||
* The max number of regions like RO(code), coherent and data required by
|
||||
* different BL stages which need to be mapped in the MMU.
|
||||
*/
|
||||
#define ARM_BL_REGIONS 3
|
||||
#define PLAT_ARM_MMAP_ENTRIES 8
|
||||
#define MAX_XLAT_TABLES 5
|
||||
#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
|
||||
ARM_BL_REGIONS)
|
||||
#define MAX_IO_DEVICES 2
|
||||
#define MAX_IO_HANDLES 3
|
||||
#define MAX_IO_BLOCK_DEVICES 1
|
||||
|
||||
/* GIC related constants */
|
||||
#define PLAT_ARM_GICD_BASE 0x1C010000
|
||||
#define PLAT_ARM_GICC_BASE 0x1C02F000
|
||||
|
||||
/* MHUv2 Secure Channel receiver and sender */
|
||||
#define PLAT_SDK700_MHU0_SEND 0x1B800000
|
||||
#define PLAT_SDK700_MHU0_RECV 0x1B810000
|
||||
|
||||
/* Timer/watchdog related constants */
|
||||
#define ARM_SYS_CNTCTL_BASE UL(0x1a200000)
|
||||
#define ARM_SYS_CNTREAD_BASE UL(0x1a210000)
|
||||
#define ARM_SYS_TIMCTL_BASE UL(0x1a220000)
|
||||
|
||||
#define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */
|
||||
|
||||
#define DIPHDA_IRQ_TZ_WDOG 32
|
||||
#define DIPHDA_IRQ_SEC_SYS_TIMER 34
|
||||
|
||||
#define PLAT_MAX_PWR_LVL 2
|
||||
/*
|
||||
* Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
|
||||
* power levels have a 1:1 mapping with the MPIDR affinity levels.
|
||||
*/
|
||||
#define ARM_PWR_LVL0 MPIDR_AFFLVL0
|
||||
#define ARM_PWR_LVL1 MPIDR_AFFLVL1
|
||||
#define ARM_PWR_LVL2 MPIDR_AFFLVL2
|
||||
|
||||
/*
|
||||
* Macros for local power states in ARM platforms encoded by State-ID field
|
||||
* within the power-state parameter.
|
||||
*/
|
||||
/* Local power state for power domains in Run state. */
|
||||
#define ARM_LOCAL_STATE_RUN U(0)
|
||||
/* Local power state for retention. Valid only for CPU power domains */
|
||||
#define ARM_LOCAL_STATE_RET U(1)
|
||||
/* Local power state for OFF/power-down. Valid for CPU and cluster
|
||||
* power domains
|
||||
*/
|
||||
#define ARM_LOCAL_STATE_OFF U(2)
|
||||
|
||||
#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
|
||||
#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
|
||||
|
||||
#define PLAT_ARM_NS_IMAGE_BASE (ARM_NS_SHARED_RAM_BASE)
|
||||
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
|
||||
/*
|
||||
* This macro defines the deepest retention state possible. A higher state
|
||||
* ID will represent an invalid or a power down state.
|
||||
*/
|
||||
#define PLAT_MAX_RET_STATE 1
|
||||
|
||||
/*
|
||||
* This macro defines the deepest power down states possible. Any state ID
|
||||
* higher than this is invalid.
|
||||
*/
|
||||
#define PLAT_MAX_OFF_STATE 2
|
||||
|
||||
#define PLATFORM_STACK_SIZE UL(0x440)
|
||||
|
||||
#define DIPHDA_EXTERNAL_FLASH MAP_REGION_FLAT( \
|
||||
PLAT_ARM_NVM_BASE, \
|
||||
PLAT_ARM_NVM_SIZE, \
|
||||
MT_DEVICE | MT_RO | MT_SECURE)
|
||||
|
||||
#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
|
||||
ARM_SHARED_RAM_BASE, \
|
||||
ARM_SHARED_RAM_SIZE, \
|
||||
MT_MEMORY | MT_RW | MT_SECURE)
|
||||
|
||||
#define ARM_MAP_NS_SHARED_RAM MAP_REGION_FLAT( \
|
||||
ARM_NS_SHARED_RAM_BASE, \
|
||||
ARM_NS_SHARED_RAM_SIZE, \
|
||||
MT_MEMORY | MT_RW | MT_NS)
|
||||
|
||||
#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
|
||||
ARM_NS_DRAM1_BASE, \
|
||||
ARM_NS_DRAM1_SIZE, \
|
||||
MT_MEMORY | MT_RW | MT_NS)
|
||||
|
||||
#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
|
||||
BL_CODE_BASE, \
|
||||
BL_CODE_END \
|
||||
- BL_CODE_BASE, \
|
||||
MT_CODE | MT_SECURE), \
|
||||
MAP_REGION_FLAT( \
|
||||
BL_RO_DATA_BASE, \
|
||||
BL_RO_DATA_END \
|
||||
- BL_RO_DATA_BASE, \
|
||||
MT_RO_DATA | MT_SECURE)
|
||||
#if USE_COHERENT_MEM
|
||||
#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
|
||||
BL_COHERENT_RAM_BASE, \
|
||||
BL_COHERENT_RAM_END \
|
||||
- BL_COHERENT_RAM_BASE, \
|
||||
MT_DEVICE | MT_RW | MT_SECURE)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Map the region for the optional device tree configuration with read and
|
||||
* write permissions
|
||||
*/
|
||||
#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \
|
||||
ARM_FW_CONFIG_BASE, \
|
||||
(ARM_FW_CONFIG_LIMIT- \
|
||||
ARM_FW_CONFIG_BASE), \
|
||||
MT_MEMORY | MT_RW | MT_SECURE)
|
||||
|
||||
#define DIPHDA_DEVICE_BASE (0x1A000000)
|
||||
#define DIPHDA_DEVICE_SIZE (0x26000000)
|
||||
#define DIPHDA_MAP_DEVICE MAP_REGION_FLAT( \
|
||||
DIPHDA_DEVICE_BASE, \
|
||||
DIPHDA_DEVICE_SIZE, \
|
||||
MT_DEVICE | MT_RW | MT_SECURE)
|
||||
|
||||
#define ARM_IRQ_SEC_PHY_TIMER 29
|
||||
|
||||
#define ARM_IRQ_SEC_SGI_0 8
|
||||
#define ARM_IRQ_SEC_SGI_1 9
|
||||
#define ARM_IRQ_SEC_SGI_2 10
|
||||
#define ARM_IRQ_SEC_SGI_3 11
|
||||
#define ARM_IRQ_SEC_SGI_4 12
|
||||
#define ARM_IRQ_SEC_SGI_5 13
|
||||
#define ARM_IRQ_SEC_SGI_6 14
|
||||
#define ARM_IRQ_SEC_SGI_7 15
|
||||
|
||||
/*
|
||||
* Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
|
||||
* terminology. On a GICv2 system or mode, the lists will be merged and treated
|
||||
* as Group 0 interrupts.
|
||||
*/
|
||||
#define ARM_G1S_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
(grp), GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
(grp), GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
(grp), GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
(grp), GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
(grp), GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
(grp), GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
(grp), GIC_INTR_CFG_EDGE)
|
||||
|
||||
#define ARM_G0_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
|
||||
GIC_INTR_CFG_EDGE)
|
||||
|
||||
/*
|
||||
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
|
||||
* terminology. On a GICv2 system or mode, the lists will be merged and treated
|
||||
* as Group 0 interrupts.
|
||||
*/
|
||||
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
|
||||
ARM_G1S_IRQ_PROPS(grp), \
|
||||
INTR_PROP_DESC(DIPHDA_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
(grp), GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(DIPHDA_IRQ_SEC_SYS_TIMER, \
|
||||
GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL)
|
||||
|
||||
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef PLAT_MACROS_S
|
||||
#define PLAT_MACROS_S
|
||||
|
||||
#include <css_macros.S>
|
||||
|
||||
/* ---------------------------------------------
|
||||
* The below required platform porting macro
|
||||
* prints out relevant platform registers
|
||||
* whenever an unhandled exception is taken in
|
||||
* BL31.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
.macro plat_crash_print_regs
|
||||
css_print_gic_regs
|
||||
.endm
|
||||
|
||||
#endif /* PLAT_MACROS_S */
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
#
|
||||
# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# Making sure the diphda platform type is specified
|
||||
ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),)
|
||||
$(error TARGET_PLATFORM must be fpga or fvp)
|
||||
endif
|
||||
|
||||
DIPHDA_CPU_LIBS +=lib/cpus/aarch64/cortex_a35.S
|
||||
|
||||
PLAT_INCLUDES := -Iplat/arm/board/diphda/common/include \
|
||||
-Iplat/arm/board/diphda/include \
|
||||
-Iinclude/plat/arm/common \
|
||||
-Iinclude/plat/arm/css/common/aarch64
|
||||
|
||||
override NEED_BL1 := no
|
||||
|
||||
override NEED_BL2 := yes
|
||||
FIP_BL2_ARGS := tb-fw
|
||||
|
||||
override NEED_BL2U := no
|
||||
override NEED_BL31 := yes
|
||||
NEED_BL32 := yes
|
||||
override NEED_BL33 := yes
|
||||
|
||||
# Include GICv2 driver files
|
||||
include drivers/arm/gic/v2/gicv2.mk
|
||||
|
||||
DIPHDA_GIC_SOURCES := ${GICV2_SOURCES} \
|
||||
plat/common/plat_gicv2.c \
|
||||
plat/arm/common/arm_gicv2.c
|
||||
|
||||
|
||||
BL2_SOURCES += plat/arm/board/diphda/common/diphda_security.c \
|
||||
plat/arm/board/diphda/common/diphda_err.c \
|
||||
plat/arm/board/diphda/common/diphda_trusted_boot.c \
|
||||
lib/utils/mem_region.c \
|
||||
plat/arm/board/diphda/common/diphda_helpers.S \
|
||||
plat/arm/board/diphda/common/diphda_plat.c \
|
||||
plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c \
|
||||
${DIPHDA_CPU_LIBS} \
|
||||
|
||||
|
||||
BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \
|
||||
lib/utils/mem_region.c \
|
||||
plat/arm/board/diphda/common/diphda_helpers.S \
|
||||
plat/arm/board/diphda/common/diphda_topology.c \
|
||||
plat/arm/board/diphda/common/diphda_security.c \
|
||||
plat/arm/board/diphda/common/diphda_plat.c \
|
||||
plat/arm/board/diphda/common/diphda_pm.c \
|
||||
${DIPHDA_CPU_LIBS} \
|
||||
${DIPHDA_GIC_SOURCES}
|
||||
|
||||
|
||||
FDT_SOURCES += plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts
|
||||
DIPHDA_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/diphda_spmc_manifest.dtb
|
||||
|
||||
# Add the SPMC manifest to FIP and specify the same to certtool
|
||||
$(eval $(call TOOL_ADD_PAYLOAD,${DIPHDA_TOS_FW_CONFIG},--tos-fw-config,${DIPHDA_TOS_FW_CONFIG}))
|
||||
|
||||
# Adding TARGET_PLATFORM as a GCC define (-D option)
|
||||
$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM})))
|
||||
|
||||
include plat/arm/common/arm_common.mk
|
||||
include plat/arm/board/common/board_common.mk
|
||||
|
|
@ -256,8 +256,10 @@ endif
|
|||
ifeq (${JUNO_AARCH32_EL3_RUNTIME},1)
|
||||
BL2_SOURCES += plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
|
||||
else
|
||||
ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),)
|
||||
BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c
|
||||
endif
|
||||
endif
|
||||
BL2_SOURCES += plat/arm/common/arm_image_load.c \
|
||||
common/desc_image_load.c
|
||||
ifeq (${SPD},opteed)
|
||||
|
|
|
|||
Loading…
Reference in New Issue