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Merge pull request #1855 from dp-arm/dp/ssbs 

Ensure proper ID register is checked for feature detection
This commit is contained in:
Antonio Niño Díaz 2019-03-05 09:52:28 +00:00 committed by GitHub
parent e70ce64c2e 6ecfda52fc
commit bf9e90c916
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 3 additions and 2 deletions
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1
include/arch/aarch64/arch_helpers.h
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@ -208,6 +208,7 @@ DEFINE_SYSREG_RW_FUNCS(par_el1)
DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1)
DEFINE_SYSREG_READ_FUNC(id_afr0_el1)
DEFINE_SYSREG_READ_FUNC(CurrentEl)

4
services/arm_arch_svc/arm_arch_svc_setup.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -41,7 +41,7 @@ static int32_t smccc_arch_features(u_register_t arg)
* PE implements architectural Speculation Store Bypass Safe
* (SSBS) feature.
*/
ssbs = (read_id_aa64pfr0_el1() >> ID_AA64PFR1_EL1_SSBS_SHIFT) &
ssbs = (read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SSBS_SHIFT) &
ID_AA64PFR1_EL1_SSBS_MASK;
/*