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Merge "intel: agilex: HMC driver calculate DDR size" into integration

This commit is contained in:
Paul Beesley 2019-08-20 09:38:32 +00:00 committed by TrustedFirmware Code Review
parent c3db45fb1d 24d16a2e40
commit bfc0c0795b
1 changed files with 8 additions and 10 deletions
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18
plat/intel/soc/agilex/soc/agilex_memory_controller.c
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@ -160,8 +160,6 @@ int init_hard_memory_controller(void)
return status;
}
/* mmio_clrbits_32(AGX_RSTMGR_BRGMODRST, AGX_RSTMGR_BRGMODRST_DDRSCH);*/
status = mem_calibration();
if (status) {
ERROR("DDR: Memory Calibration Failed\n");
@ -169,7 +167,6 @@ int init_hard_memory_controller(void)
}
configure_hmc_adaptor_regs();
/* configure_ddr_sched_ctrl_regs();*/
return 0;
}
@ -359,17 +356,18 @@ void configure_hmc_adaptor_regs(void)
mmio_write_32(AGX_MPFE_HMC_ADP(ADP_DRAMADDRWIDTH), data);
/* Enable nonsecure access to DDR */
mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT,
AGX_DDR_SIZE - 1);
mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT,
0x1f);
data = get_physical_dram_size();
mmio_write_32(AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT,
AGX_DDR_SIZE - 1);
if (data < AGX_DDR_SIZE)
data = AGX_DDR_SIZE;
mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT, data - 1);
mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT, 0x1f);
mmio_write_32(AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT, data - 1);
mmio_write_32(AGX_SOC_NOC_FW_DDR_SCR_ENABLESET, BIT(0) | BIT(8));
/* ECC enablement */
data = mmio_read_32(AGX_MPFE_IOHMC_REG_CTRLCFG1);
if (data & (1 << AGX_IOHMC_CTRLCFG1_ENABLE_ECC_OFST)) {