Perform a cache flush after ENTER PSCI timestamp capture
Without an explicit cache flush, the next timestamp captured might have a bogus value. This can happen if the following operations happen in order, on a CPU that's being powered down. 1) ENTER PSCI timestamp is captured with caches enabled. 2) The next timestamp (ENTER_HW_LOW_PWR) is captured with caches disabled. 3) On a system that uses a write-back cache configuration, the cache line that holds the PMF timestamps is evicted. After step 1), the ENTER_PSCI timestamp is cached and not in main memory. After step 2), the ENTER_HW_LOW_PWR timestamp is stored in main memory. Before the CPU power down happens, the hardware evicts the cache line that contains the PMF timestamps for this service. As a result, the timestamp captured in step 2) is overwritten with a bogus value. Change-Id: Ic1bd816498d1a6d4dc16540208ed3a5efe43f529 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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@ -81,9 +81,14 @@ uintptr_t std_svc_smc_handler(uint32_t smc_fid,
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uint64_t ret;
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#if ENABLE_RUNTIME_INSTRUMENTATION
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/*
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* Flush cache line so that even if CPU power down happens
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* the timestamp update is reflected in memory.
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*/
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PMF_WRITE_TIMESTAMP(rt_instr_svc,
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RT_INSTR_ENTER_PSCI,
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PMF_NO_CACHE_MAINT,
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PMF_CACHE_MAINT,
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get_cpu_data(cpu_data_pmf_ts[CPU_DATA_PMF_TS0_IDX]));
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#endif
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