Driver for 16550 UART interface
This patch adds driver for the 16550 UART interface. The driver is exposed as a console, which platforms can use to dump their boot/crash logs. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar
parent
aaa48a86b9
commit
c13b2e32f1
1
Makefile
1
Makefile
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@ -212,6 +212,7 @@ INCLUDES += -Iinclude/bl31 \
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-Iinclude/drivers \
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-Iinclude/drivers/arm \
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-Iinclude/drivers/io \
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-Iinclude/drivers/ti/uart \
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-Iinclude/lib \
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-Iinclude/lib/aarch64 \
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-Iinclude/lib/cpus/aarch64 \
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@ -0,0 +1,155 @@
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <uart_16550.h>
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.globl console_core_init
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.globl console_core_putc
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.globl console_core_getc
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/* -----------------------------------------------
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* int console_core_init(unsigned long base_addr,
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* unsigned int uart_clk, unsigned int baud_rate)
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* Function to initialize the console without a
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* C Runtime to print debug information. This
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* function will be accessed by console_init and
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* crash reporting.
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* In: x0 - console base address
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* w1 - Uart clock in Hz
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* w2 - Baud rate
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* Out: return 1 on success
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* Clobber list : x1, x2, x3
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* -----------------------------------------------
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*/
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func console_core_init
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/* Check the input base address */
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cbz x0, init_fail
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/* Check baud rate and uart clock for sanity */
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cbz w1, init_fail
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cbz w2, init_fail
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/* Program the baudrate */
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/* Divisor = Uart clock / (16 * baudrate) */
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lsl w2, w2, #4
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udiv w2, w1, w2
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and w1, w2, #0xff /* w1 = DLL */
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lsr w2, w2, #8
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and w2, w2, #0xff /* w2 = DLLM */
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ldr w3, [x0, #UARTLCR]
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orr w3, w3, #UARTLCR_DLAB
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str w3, [x0, #UARTLCR] /* enable DLL, DLLM programming */
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str w1, [x0, #UARTDLL] /* program DLL */
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str w2, [x0, #UARTDLLM] /* program DLLM */
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mov w2, #~UARTLCR_DLAB
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and w3, w3, w2
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str w3, [x0, #UARTLCR] /* disable DLL, DLLM programming */
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/* 8n1 */
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mov w3, #3
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str w3, [x0, #UARTLCR]
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/* no interrupt */
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mov w3, #0
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str w3, [x0, #UARTIER]
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/* enable fifo, DMA */
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mov w3, #(UARTFCR_FIFOEN | UARTFCR_DMAEN)
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str w3, [x0, #UARTFCR]
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/* DTR + RTS */
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mov w3, #3
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str w3, [x0, #UARTMCR]
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mov w0, #1
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init_fail:
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ret
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endfunc console_core_init
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/* --------------------------------------------------------
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* int console_core_putc(int c, unsigned int base_addr)
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* Function to output a character over the console. It
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* returns the character printed on success or -1 on error.
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* In : w0 - character to be printed
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* x1 - console base address
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* Out : return -1 on error else return character.
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* Clobber list : x2
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* --------------------------------------------------------
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*/
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func console_core_putc
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/* Check the input parameter */
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cbz x1, putc_error
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/* Prepend '\r' to '\n' */
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cmp w0, #0xA
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b.ne 2f
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/* Check if the transmit FIFO is full */
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1: ldr w2, [x1, #UARTLSR]
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and w2, w2, #(UARTLSR_TEMT | UARTLSR_THRE)
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cmp w2, #(UARTLSR_TEMT | UARTLSR_THRE)
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b.ne 1b
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mov w2, #0xD /* '\r' */
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str w2, [x1, #UARTTX]
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ldr w2, [x1, #UARTFCR]
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orr w2, w2, #UARTFCR_TXCLR
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str w2, [x1, #UARTFCR]
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/* Check if the transmit FIFO is full */
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2: ldr w2, [x1, #UARTLSR]
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and w2, w2, #(UARTLSR_TEMT | UARTLSR_THRE)
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cmp w2, #(UARTLSR_TEMT | UARTLSR_THRE)
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b.ne 2b
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str w0, [x1, #UARTTX]
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ldr w2, [x1, #UARTFCR]
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orr w2, w2, #UARTFCR_TXCLR
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str w2, [x1, #UARTFCR]
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ret
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putc_error:
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mov w0, #-1
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ret
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endfunc console_core_putc
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/* ---------------------------------------------
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* int console_core_getc(void)
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* Function to get a character from the console.
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* It returns the character grabbed on success
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* or -1 on error.
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* In : w0 - console base address
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* Out : return -1 on error else return character.
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func console_core_getc
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/* Check if the receive FIFO is empty */
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1: ldr w1, [x0, #UARTLSR]
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tbz w1, #UARTLSR_RDR, 1b
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ldr w0, [x0, #UARTRX]
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ret
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getc_error:
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mov w0, #-1
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ret
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endfunc console_core_getc
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@ -0,0 +1,93 @@
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __UART_16550_H__
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#define __UART_16550_H__
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/* UART16550 Registers */
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#define UARTTX 0x0
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#define UARTRX 0x0
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#define UARTDLL 0x0
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#define UARTIER 0x4
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#define UARTDLLM 0x4
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#define UARTIIR 0x8
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#define UARTFCR 0x8
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#define UARTLCR 0xc
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#define UARTMCR 0x10
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#define UARTLSR 0x14
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#define UARTMSR 0x18
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#define UARTSPR 0x1c
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#define UARTCSR 0x20
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#define UARTRXFIFOCFG 0x24
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#define UARTMIE 0x28
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#define UARTVNDR 0x2c
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#define UARTASR 0x3c
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/* FIFO Control Register bits */
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#define UARTFCR_FIFOMD_16450 (0 << 6)
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#define UARTFCR_FIFOMD_16550 (1 << 6)
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#define UARTFCR_RXTRIG_1 (0 << 6)
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#define UARTFCR_RXTRIG_4 (1 << 6)
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#define UARTFCR_RXTRIG_8 (2 << 6)
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#define UARTFCR_RXTRIG_16 (3 << 6)
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#define UARTFCR_TXTRIG_1 (0 << 4)
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#define UARTFCR_TXTRIG_4 (1 << 4)
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#define UARTFCR_TXTRIG_8 (2 << 4)
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#define UARTFCR_TXTRIG_16 (3 << 4)
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#define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */
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#define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */
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#define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */
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#define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */
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/* Line Control Register bits */
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#define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */
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#define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */
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#define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */
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#define UARTLCR_EVEN (1 << 4) /* Even Parity Format */
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#define UARTLCR_PAR (1 << 3) /* Parity */
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#define UARTLCR_STOP (1 << 2) /* Stop Bit */
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#define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */
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#define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */
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#define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */
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#define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */
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/* Line Status Register bits */
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#define UARTLSR_RXFIFOEMT (1 << 9) /* Rx Fifo Empty */
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#define UARTLSR_TXFIFOFULL (1 << 8) /* Tx Fifo Full */
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#define UARTLSR_RXFIFOERR (1 << 7) /* Rx Fifo Error */
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#define UARTLSR_TEMT (1 << 6) /* Tx Shift Register Empty */
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#define UARTLSR_THRE (1 << 5) /* Tx Holding Register Empty */
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#define UARTLSR_BRK (1 << 4) /* Break Condition Detected */
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#define UARTLSR_FERR (1 << 3) /* Framing Error */
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#define UARTLSR_PERR (1 << 3) /* Parity Error */
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#define UARTLSR_OVRF (1 << 2) /* Rx Overrun Error */
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#define UARTLSR_RDR (1 << 2) /* Rx Data Ready */
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#endif /* __UART_16550_H__ */
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