Move console functions out of pl011.c
This commit isolates the accessor functions in pl011.c and builds a wrapper layer for console functions. This also modifies the console driver to use the pl011 FIFO. Fixes ARM-software/tf-issues#63 Change-Id: I3b402171cd14a927831bf5e5d4bb310b6da0e9a8
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08c7ed0fe8
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@ -28,62 +28,15 @@
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* POSSIBILITY OF SUCH DAMAGE.
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#include <stdio.h>
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#include <console.h>
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#include <platform.h>
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#include <platform.h>
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#include <pl011.h>
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#include <pl011.h>
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#include <assert.h>
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static unsigned long uart_base = PL011_BASE;
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void pl011_setbaudrate(unsigned long base_addr, unsigned int baudrate)
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/*
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* TODO: Console init functions shoule be in a console.c. This file should
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* only contain the pl011 accessors.
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*/
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void console_init(unsigned long base_addr)
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{
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{
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unsigned int divisor;
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unsigned int divisor;
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assert(baudrate);
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/* Initialise internal base address variable */
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divisor = (PL011_CLK_IN_HZ * 4) / baudrate;
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uart_base = base_addr;
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pl011_write_ibrd(base_addr, divisor >> 6);
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pl011_write_fbrd(base_addr, divisor & 0x3F);
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/* Baud Rate */
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#if defined(PL011_INTEGER) && defined(PL011_FRACTIONAL)
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mmio_write_32(uart_base + UARTIBRD, PL011_INTEGER);
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mmio_write_32(uart_base + UARTFBRD, PL011_FRACTIONAL);
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#else
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divisor = (PL011_CLK_IN_HZ * 4) / PL011_BAUDRATE;
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mmio_write_32(uart_base + UARTIBRD, divisor >> 6);
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mmio_write_32(uart_base + UARTFBRD, divisor & 0x3F);
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#endif
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mmio_write_32(uart_base + UARTLCR_H, PL011_LINE_CONTROL);
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/* Clear any pending errors */
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mmio_write_32(uart_base + UARTECR, 0);
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/* Enable tx, rx, and uart overall */
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mmio_write_32(uart_base + UARTCR,
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PL011_UARTCR_RXE | PL011_UARTCR_TXE |
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PL011_UARTCR_UARTEN);
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}
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int console_putc(int c)
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{
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if (c == '\n') {
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console_putc('\r');
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}
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while ((mmio_read_32(uart_base + UARTFR) & PL011_UARTFR_TXFE) == 0)
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;
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mmio_write_32(uart_base + UARTDR, c);
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return c;
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}
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int console_getc(void)
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{
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while ((mmio_read_32(uart_base + UARTFR) & PL011_UARTFR_RXFE) != 0)
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;
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return mmio_read_32(uart_base + UARTDR);
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}
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}
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@ -104,4 +104,58 @@
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#define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */
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#define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */
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#define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */
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#define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */
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/*******************************************************************************
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* Pl011 CPU interface accessors for writing registers
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******************************************************************************/
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static inline void pl011_write_ibrd(unsigned int base, unsigned int val)
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{
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mmio_write_32(base + UARTIBRD, val);
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}
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static inline void pl011_write_fbrd(unsigned int base, unsigned int val)
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{
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mmio_write_32(base + UARTFBRD, val);
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}
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static inline void pl011_write_lcr_h(unsigned int base, unsigned int val)
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{
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mmio_write_32(base + UARTLCR_H, val);
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}
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static inline void pl011_write_ecr(unsigned int base, unsigned int val)
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{
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mmio_write_32(base + UARTECR, val);
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}
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static inline void pl011_write_cr(unsigned int base, unsigned int val)
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{
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mmio_write_32(base + UARTCR, val);
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}
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static inline void pl011_write_dr(unsigned int base, unsigned int val)
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{
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mmio_write_32(base + UARTDR, val);
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}
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/*******************************************************************************
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* Pl011 CPU interface accessors for reading registers
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******************************************************************************/
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static inline unsigned int pl011_read_fr(unsigned int base)
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{
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return mmio_read_32(base + UARTFR);
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}
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static inline unsigned int pl011_read_dr(unsigned int base)
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{
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return mmio_read_32(base + UARTDR);
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}
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/*******************************************************************************
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* Function prototypes
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******************************************************************************/
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void pl011_setbaudrate(unsigned long base_addr, unsigned int baudrate);
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#endif /* __PL011_H__ */
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#endif /* __PL011_H__ */
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@ -0,0 +1,77 @@
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/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <console.h>
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#include <platform.h>
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#include <pl011.h>
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static unsigned long uart_base = PL011_BASE;
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void console_init(unsigned long base_addr)
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{
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/* Initialise internal base address variable */
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uart_base = base_addr;
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/* Baud Rate */
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#if defined(PL011_INTEGER) && defined(PL011_FRACTIONAL)
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pl011_write_ibrd(uart_base, PL011_INTEGER);
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pl011_write_fbrd(uart_base, PL011_FRACTIONAL);
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#else
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pl011_setbaudrate(uart_base, PL011_BAUDRATE);
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#endif
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pl011_write_lcr_h(uart_base, PL011_LINE_CONTROL);
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/* Clear any pending errors */
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pl011_write_ecr(uart_base, 0);
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/* Enable tx, rx, and uart overall */
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pl011_write_cr(uart_base, PL011_UARTCR_RXE | PL011_UARTCR_TXE |
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PL011_UARTCR_UARTEN);
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}
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int console_putc(int c)
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{
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if (c == '\n')
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console_putc('\r');
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while ((pl011_read_fr(uart_base) & PL011_UARTFR_TXFF) == 1)
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;
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pl011_write_dr(uart_base, c);
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return c;
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}
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int console_getc(void)
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{
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while ((pl011_read_fr(uart_base) & PL011_UARTFR_RXFE) != 0)
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;
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return pl011_read_dr(uart_base);
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}
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@ -29,10 +29,12 @@
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#
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#
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PLAT_INCLUDES := -Idrivers/arm/interconnect/cci-400 \
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PLAT_INCLUDES := -Idrivers/arm/interconnect/cci-400 \
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-Idrivers/console \
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-Idrivers/arm/peripherals/pl011 \
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-Idrivers/arm/peripherals/pl011 \
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-Idrivers/power
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-Idrivers/power
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PLAT_BL1_C_VPATH := drivers/arm/interconnect/cci-400 \
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PLAT_BL1_C_VPATH := drivers/arm/interconnect/cci-400 \
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drivers/console \
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drivers/arm/peripherals/pl011 \
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drivers/arm/peripherals/pl011 \
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lib/arch/${ARCH} \
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lib/arch/${ARCH} \
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lib/semihosting \
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lib/semihosting \
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PLAT_BL1_S_VPATH := lib/semihosting/${ARCH}
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PLAT_BL1_S_VPATH := lib/semihosting/${ARCH}
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PLAT_BL2_C_VPATH := drivers/arm/interconnect/cci-400 \
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PLAT_BL2_C_VPATH := drivers/arm/interconnect/cci-400 \
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drivers/console \
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drivers/arm/peripherals/pl011 \
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drivers/arm/peripherals/pl011 \
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lib/arch/${ARCH} \
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lib/arch/${ARCH} \
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lib/stdlib \
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lib/stdlib \
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PLAT_BL2_S_VPATH := lib/semihosting/${ARCH}
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PLAT_BL2_S_VPATH := lib/semihosting/${ARCH}
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PLAT_BL31_C_VPATH := drivers/arm/interconnect/cci-400 \
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PLAT_BL31_C_VPATH := drivers/arm/interconnect/cci-400 \
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drivers/console \
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drivers/arm/peripherals/pl011 \
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drivers/arm/peripherals/pl011 \
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lib/arch/${ARCH} \
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lib/arch/${ARCH} \
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lib/semihosting \
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lib/semihosting \
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PLAT_BL_COMMON_SOURCES := semihosting_call.S \
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PLAT_BL_COMMON_SOURCES := semihosting_call.S \
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mmio.c \
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mmio.c \
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console.c \
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pl011.c \
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pl011.c \
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semihosting.c \
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semihosting.c \
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sysreg_helpers.S \
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sysreg_helpers.S \
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