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Merge "Enable -Wredundant-decls warning check" into integration

This commit is contained in:
Soby Mathew 2020-01-29 09:50:05 +00:00 committed by TrustedFirmware Code Review
parent b012454d82 ca661a0092
commit c1f118f1a7
11 changed files with 43 additions and 52 deletions
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3
Makefile
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@ -255,7 +255,7 @@ ASFLAGS_aarch64 = $(march64-directive)
# General warnings
WARNINGS := -Wall -Wmissing-include-dirs -Wunused \
-Wdisabled-optimization -Wvla -Wshadow \
-Wno-unused-parameter
-Wno-unused-parameter -Wredundant-decls
# Additional warnings
# Level 1
@ -274,7 +274,6 @@ WARNING3 += -Wcast-qual
WARNING3 += -Wconversion
WARNING3 += -Wpacked
WARNING3 += -Wpointer-arith
WARNING3 += -Wredundant-decls
WARNING3 += -Wswitch-default
ifeq (${W},1)

13
plat/imx/imx8qm/imx8qm_bl31_setup.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -27,12 +27,13 @@
#include <sci/sci.h>
#include <sec_rsrc.h>
IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START);
IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END);
IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START);
IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END);
static const unsigned long BL31_COHERENT_RAM_START = BL_COHERENT_RAM_BASE;
static const unsigned long BL31_COHERENT_RAM_END = BL_COHERENT_RAM_END;
static const unsigned long BL31_RO_START = BL_CODE_BASE;
static const unsigned long BL31_RO_END = BL_CODE_END;
static const unsigned long BL31_RW_END = BL_END;
IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END);
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;

13
plat/imx/imx8qx/imx8qx_bl31_setup.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -27,12 +27,13 @@
#include <sci/sci.h>
#include <sec_rsrc.h>
IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START);
IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END);
IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START);
IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END);
static const unsigned long BL31_COHERENT_RAM_START = BL_COHERENT_RAM_BASE;
static const unsigned long BL31_COHERENT_RAM_END = BL_COHERENT_RAM_END;
static const unsigned long BL31_RO_START = BL_CODE_BASE;
static const unsigned long BL31_RO_END = BL_CODE_END;
static const unsigned long BL31_RW_END = BL_END;
IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END);
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;

3
plat/intel/soc/common/include/socfpga_system_manager.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -106,7 +106,6 @@
#define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
#define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
void enable_nonsecure_access(void);
void enable_ns_peripheral_access(void);
void enable_ns_bridge_access(void);

13
plat/nvidia/tegra/common/tegra_bl31_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -42,11 +42,12 @@ extern void memcpy16(void *dest, const void *src, unsigned int length);
******************************************************************************/
IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START);
IMPORT_SYM(uint64_t, __RW_END__, BL31_RW_END);
IMPORT_SYM(uint64_t, __RODATA_START__, BL31_RODATA_BASE);
IMPORT_SYM(uint64_t, __RODATA_END__, BL31_RODATA_END);
IMPORT_SYM(uint64_t, __TEXT_START__, TEXT_START);
IMPORT_SYM(uint64_t, __TEXT_END__, TEXT_END);
static const uint64_t BL31_RW_END = BL_END;
static const uint64_t BL31_RODATA_BASE = BL_RO_DATA_BASE;
static const uint64_t BL31_RODATA_END = BL_RO_DATA_END;
static const uint64_t TEXT_START = BL_CODE_BASE;
static const uint64_t TEXT_END = BL_CODE_END;
extern uint64_t tegra_bl31_phys_base;

1
plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
View File

@ -53,7 +53,6 @@ uint64_t nvg_get_cstate_stat_query_value(void);
int32_t nvg_is_sc7_allowed(void);
int32_t nvg_online_core(uint32_t core);
int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
int32_t nvg_roc_clean_cache_trbits(void);
int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
int32_t nvg_roc_clean_cache_trbits(void);
void nvg_enable_strict_checking_mode(void);

17
plat/renesas/rcar/bl2_plat_setup.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -39,12 +39,19 @@
#include "rcar_version.h"
#include "rom_api.h"
IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE)
IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT)
#if RCAR_BL2_DCACHE == 1
/*
* Following symbols are only used during plat_arch_setup() only
* when RCAR_BL2_DCACHE is enabled.
*/
static const uint64_t BL2_RO_BASE = BL_CODE_BASE;
static const uint64_t BL2_RO_LIMIT = BL_CODE_END;
#if USE_COHERENT_MEM
IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE)
IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT)
static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
#endif
#endif
extern void plat_rcar_gic_driver_init(void);

10
plat/renesas/rcar/bl31_plat_setup.c
View File

@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -22,12 +22,12 @@
#include "rcar_private.h"
#include "rcar_version.h"
IMPORT_SYM(uint64_t, __RO_START__, BL31_RO_BASE)
IMPORT_SYM(uint64_t, __RO_END__, BL31_RO_LIMIT)
static const uint64_t BL31_RO_BASE = BL_CODE_BASE;
static const uint64_t BL31_RO_LIMIT = BL_CODE_END;
#if USE_COHERENT_MEM
IMPORT_SYM(uint64_t, __COHERENT_RAM_START__, BL31_COHERENT_RAM_BASE)
IMPORT_SYM(uint64_t, __COHERENT_RAM_END__, BL31_COHERENT_RAM_LIMIT)
static const uint64_t BL31_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
static const uint64_t BL31_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
#endif
extern void plat_rcar_gic_driver_init(void);

18
plat/st/stm32mp1/include/stm32mp1_boot_device.h
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@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP1_BOOT_DEVICE_H
#define STM32MP1_BOOT_DEVICE_H
#include <drivers/raw_nand.h>
#include <drivers/spi_nand.h>
#include <drivers/spi_nor.h>
int plat_get_raw_nand_data(struct rawnand_device *device);
int plat_get_spi_nand_data(struct spinand_device *device);
int plat_get_nor_data(struct nor_device *device);
#endif /* STM32MP1_BOOT_DEVICE_H */

3
plat/st/stm32mp1/stm32mp1_boot_device.c
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@ -7,6 +7,9 @@
#include <errno.h>
#include <drivers/nand.h>
#include <drivers/raw_nand.h>
#include <drivers/spi_nand.h>
#include <drivers/spi_nor.h>
#include <lib/utils.h>
#include <plat/common/platform.h>

1
plat/st/stm32mp1/stm32mp1_def.h
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@ -23,7 +23,6 @@
#include <stm32mp_common.h>
#include <stm32mp_dt.h>
#include <stm32mp_shres_helpers.h>
#include <stm32mp1_boot_device.h>
#include <stm32mp1_dbgmcu.h>
#include <stm32mp1_private.h>
#endif