Merge "Enable -Wredundant-decls warning check" into integration
This commit is contained in:
commit
c1f118f1a7
3
Makefile
3
Makefile
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@ -255,7 +255,7 @@ ASFLAGS_aarch64 = $(march64-directive)
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# General warnings
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# General warnings
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WARNINGS := -Wall -Wmissing-include-dirs -Wunused \
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WARNINGS := -Wall -Wmissing-include-dirs -Wunused \
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-Wdisabled-optimization -Wvla -Wshadow \
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-Wdisabled-optimization -Wvla -Wshadow \
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-Wno-unused-parameter
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-Wno-unused-parameter -Wredundant-decls
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# Additional warnings
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# Additional warnings
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# Level 1
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# Level 1
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@ -274,7 +274,6 @@ WARNING3 += -Wcast-qual
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WARNING3 += -Wconversion
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WARNING3 += -Wconversion
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WARNING3 += -Wpacked
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WARNING3 += -Wpacked
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WARNING3 += -Wpointer-arith
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WARNING3 += -Wpointer-arith
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WARNING3 += -Wredundant-decls
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WARNING3 += -Wswitch-default
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WARNING3 += -Wswitch-default
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ifeq (${W},1)
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ifeq (${W},1)
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -27,12 +27,13 @@
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#include <sci/sci.h>
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#include <sci/sci.h>
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#include <sec_rsrc.h>
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#include <sec_rsrc.h>
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IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START);
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static const unsigned long BL31_COHERENT_RAM_START = BL_COHERENT_RAM_BASE;
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IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END);
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static const unsigned long BL31_COHERENT_RAM_END = BL_COHERENT_RAM_END;
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IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START);
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static const unsigned long BL31_RO_START = BL_CODE_BASE;
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IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END);
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static const unsigned long BL31_RO_END = BL_CODE_END;
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static const unsigned long BL31_RW_END = BL_END;
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IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
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IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
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IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END);
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -27,12 +27,13 @@
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#include <sci/sci.h>
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#include <sci/sci.h>
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#include <sec_rsrc.h>
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#include <sec_rsrc.h>
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IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START);
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static const unsigned long BL31_COHERENT_RAM_START = BL_COHERENT_RAM_BASE;
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IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END);
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static const unsigned long BL31_COHERENT_RAM_END = BL_COHERENT_RAM_END;
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IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START);
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static const unsigned long BL31_RO_START = BL_CODE_BASE;
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IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END);
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static const unsigned long BL31_RO_END = BL_CODE_END;
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static const unsigned long BL31_RW_END = BL_END;
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IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
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IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
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IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END);
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -106,7 +106,6 @@
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#define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
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#define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
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#define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
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#define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
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void enable_nonsecure_access(void);
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void enable_ns_peripheral_access(void);
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void enable_ns_peripheral_access(void);
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void enable_ns_bridge_access(void);
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void enable_ns_bridge_access(void);
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -42,11 +42,12 @@ extern void memcpy16(void *dest, const void *src, unsigned int length);
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******************************************************************************/
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******************************************************************************/
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IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START);
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IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START);
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IMPORT_SYM(uint64_t, __RW_END__, BL31_RW_END);
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IMPORT_SYM(uint64_t, __RODATA_START__, BL31_RODATA_BASE);
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static const uint64_t BL31_RW_END = BL_END;
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IMPORT_SYM(uint64_t, __RODATA_END__, BL31_RODATA_END);
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static const uint64_t BL31_RODATA_BASE = BL_RO_DATA_BASE;
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IMPORT_SYM(uint64_t, __TEXT_START__, TEXT_START);
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static const uint64_t BL31_RODATA_END = BL_RO_DATA_END;
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IMPORT_SYM(uint64_t, __TEXT_END__, TEXT_END);
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static const uint64_t TEXT_START = BL_CODE_BASE;
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static const uint64_t TEXT_END = BL_CODE_END;
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extern uint64_t tegra_bl31_phys_base;
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extern uint64_t tegra_bl31_phys_base;
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@ -53,7 +53,6 @@ uint64_t nvg_get_cstate_stat_query_value(void);
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int32_t nvg_is_sc7_allowed(void);
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int32_t nvg_is_sc7_allowed(void);
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int32_t nvg_online_core(uint32_t core);
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int32_t nvg_online_core(uint32_t core);
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int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
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int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
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int32_t nvg_roc_clean_cache_trbits(void);
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int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
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int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
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int32_t nvg_roc_clean_cache_trbits(void);
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int32_t nvg_roc_clean_cache_trbits(void);
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void nvg_enable_strict_checking_mode(void);
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void nvg_enable_strict_checking_mode(void);
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -39,12 +39,19 @@
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#include "rcar_version.h"
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#include "rcar_version.h"
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#include "rom_api.h"
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#include "rom_api.h"
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IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE)
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#if RCAR_BL2_DCACHE == 1
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IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT)
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/*
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* Following symbols are only used during plat_arch_setup() only
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* when RCAR_BL2_DCACHE is enabled.
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*/
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static const uint64_t BL2_RO_BASE = BL_CODE_BASE;
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static const uint64_t BL2_RO_LIMIT = BL_CODE_END;
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#if USE_COHERENT_MEM
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#if USE_COHERENT_MEM
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IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE)
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static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
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IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT)
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static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
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#endif
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#endif
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#endif
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extern void plat_rcar_gic_driver_init(void);
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extern void plat_rcar_gic_driver_init(void);
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@ -1,6 +1,6 @@
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/*
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/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -22,12 +22,12 @@
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#include "rcar_private.h"
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#include "rcar_private.h"
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#include "rcar_version.h"
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#include "rcar_version.h"
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IMPORT_SYM(uint64_t, __RO_START__, BL31_RO_BASE)
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static const uint64_t BL31_RO_BASE = BL_CODE_BASE;
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IMPORT_SYM(uint64_t, __RO_END__, BL31_RO_LIMIT)
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static const uint64_t BL31_RO_LIMIT = BL_CODE_END;
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#if USE_COHERENT_MEM
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#if USE_COHERENT_MEM
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IMPORT_SYM(uint64_t, __COHERENT_RAM_START__, BL31_COHERENT_RAM_BASE)
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static const uint64_t BL31_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
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IMPORT_SYM(uint64_t, __COHERENT_RAM_END__, BL31_COHERENT_RAM_LIMIT)
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static const uint64_t BL31_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
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#endif
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#endif
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extern void plat_rcar_gic_driver_init(void);
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extern void plat_rcar_gic_driver_init(void);
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@ -1,18 +0,0 @@
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/*
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* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32MP1_BOOT_DEVICE_H
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#define STM32MP1_BOOT_DEVICE_H
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#include <drivers/raw_nand.h>
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#include <drivers/spi_nand.h>
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#include <drivers/spi_nor.h>
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int plat_get_raw_nand_data(struct rawnand_device *device);
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int plat_get_spi_nand_data(struct spinand_device *device);
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int plat_get_nor_data(struct nor_device *device);
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#endif /* STM32MP1_BOOT_DEVICE_H */
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@ -7,6 +7,9 @@
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#include <errno.h>
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#include <errno.h>
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#include <drivers/nand.h>
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#include <drivers/nand.h>
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#include <drivers/raw_nand.h>
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#include <drivers/spi_nand.h>
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#include <drivers/spi_nor.h>
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#include <lib/utils.h>
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#include <lib/utils.h>
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#include <plat/common/platform.h>
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#include <plat/common/platform.h>
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@ -23,7 +23,6 @@
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#include <stm32mp_common.h>
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#include <stm32mp_common.h>
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#include <stm32mp_dt.h>
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#include <stm32mp_dt.h>
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#include <stm32mp_shres_helpers.h>
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#include <stm32mp_shres_helpers.h>
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#include <stm32mp1_boot_device.h>
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#include <stm32mp1_dbgmcu.h>
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#include <stm32mp1_dbgmcu.h>
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#include <stm32mp1_private.h>
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#include <stm32mp1_private.h>
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#endif
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#endif
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