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Merge pull request #684 from rockchip-linux/add-sdram-for-rk3399 

rockchip: add dram driver for rk3399
This commit is contained in:
davidcunado-arm 2016-08-25 13:56:25 +01:00 committed by GitHub
parent 079e522d39 863edcea43
commit c2229abd75
9 changed files with 5220 additions and 1 deletions
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364
plat/rockchip/rk3399/drivers/dram/dcf_code.inc Normal file
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plat/rockchip/rk3399/drivers/dram/dram.c Normal file
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/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SOC_ROCKCHIP_RK3399_SDRAM_H__
#define __SOC_ROCKCHIP_RK3399_SDRAM_H__
struct rk3399_ddr_cic_regs {
uint32_t cic_ctrl0;
uint32_t cic_ctrl1;
uint32_t cic_idle_th;
uint32_t cic_cg_wait_th;
uint32_t cic_status0;
uint32_t cic_status1;
uint32_t cic_ctrl2;
uint32_t cic_ctrl3;
uint32_t cic_ctrl4;
};
/* DENALI_CTL_00 */
#define START (1)
/* DENALI_CTL_68 */
#define PWRUP_SREFRESH_EXIT (1 << 16)
/* DENALI_CTL_274 */
#define MEM_RST_VALID (1)
struct rk3399_ddr_pctl_regs {
uint32_t denali_ctl[332];
};
struct rk3399_ddr_publ_regs {
uint32_t denali_phy[959];
};
#define PHY_DRV_ODT_Hi_Z (0x0)
#define PHY_DRV_ODT_240 (0x1)
#define PHY_DRV_ODT_120 (0x8)
#define PHY_DRV_ODT_80 (0x9)
#define PHY_DRV_ODT_60 (0xc)
#define PHY_DRV_ODT_48 (0xd)
#define PHY_DRV_ODT_40 (0xe)
#define PHY_DRV_ODT_34_3 (0xf)
struct rk3399_ddr_pi_regs {
uint32_t denali_pi[200];
};
union noc_ddrtiminga0 {
uint32_t d32;
struct {
unsigned acttoact : 6;
unsigned reserved0 : 2;
unsigned rdtomiss : 6;
unsigned reserved1 : 2;
unsigned wrtomiss : 6;
unsigned reserved2 : 2;
unsigned readlatency : 8;
} b;
};
union noc_ddrtimingb0 {
uint32_t d32;
struct {
unsigned rdtowr : 5;
unsigned reserved0 : 3;
unsigned wrtord : 5;
unsigned reserved1 : 3;
unsigned rrd : 4;
unsigned reserved2 : 4;
unsigned faw : 6;
unsigned reserved3 : 2;
} b;
};
union noc_ddrtimingc0 {
uint32_t d32;
struct {
unsigned burstpenalty : 4;
unsigned reserved0 : 4;
unsigned wrtomwr : 6;
unsigned reserved1 : 18;
} b;
};
union noc_devtodev0 {
uint32_t d32;
struct {
unsigned busrdtord : 3;
unsigned reserved0 : 1;
unsigned busrdtowr : 3;
unsigned reserved1 : 1;
unsigned buswrtord : 3;
unsigned reserved2 : 1;
unsigned buswrtowr : 3;
unsigned reserved3 : 17;
} b;
};
union noc_ddrmode {
uint32_t d32;
struct {
unsigned autoprecharge : 1;
unsigned bypassfiltering : 1;
unsigned fawbank : 1;
unsigned burstsize : 2;
unsigned mwrsize : 2;
unsigned reserved2 : 1;
unsigned forceorder : 8;
unsigned forceorderstate : 8;
unsigned reserved3 : 8;
} b;
};
struct rk3399_msch_regs {
uint32_t coreid;
uint32_t revisionid;
uint32_t ddrconf;
uint32_t ddrsize;
union noc_ddrtiminga0 ddrtiminga0;
union noc_ddrtimingb0 ddrtimingb0;
union noc_ddrtimingc0 ddrtimingc0;
union noc_devtodev0 devtodev0;
uint32_t reserved0[(0x110-0x20)/4];
union noc_ddrmode ddrmode;
uint32_t reserved1[(0x1000-0x114)/4];
uint32_t agingx0;
};
struct rk3399_msch_timings {
union noc_ddrtiminga0 ddrtiminga0;
union noc_ddrtimingb0 ddrtimingb0;
union noc_ddrtimingc0 ddrtimingc0;
union noc_devtodev0 devtodev0;
union noc_ddrmode ddrmode;
uint32_t agingx0;
};
#if 1
struct rk3399_sdram_channel {
unsigned char rank;
/* col = 0, means this channel is invalid */
unsigned char col;
/* 3:8bank, 2:4bank */
unsigned char bk;
/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
unsigned char bw;
/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
unsigned char dbw;
/* row_3_4 = 1: 6Gb or 12Gb die
* row_3_4 = 0: normal die, power of 2
*/
unsigned char row_3_4;
unsigned char cs0_row;
unsigned char cs1_row;
uint32_t ddrconfig;
struct rk3399_msch_timings noc_timings;
};
struct rk3399_sdram_params {
struct rk3399_sdram_channel ch[2];
uint32_t ddr_freq;
unsigned char dramtype;
unsigned char num_channels;
unsigned char stride;
unsigned char odt;
struct rk3399_ddr_pctl_regs pctl_regs;
struct rk3399_ddr_pi_regs pi_regs;
struct rk3399_ddr_publ_regs phy_regs;
};
#endif
struct rk3399_sdram_channel_config {
uint32_t bus_width;
uint32_t cs_cnt;
uint32_t cs0_row;
uint32_t cs1_row;
uint32_t bank;
uint32_t col;
uint32_t each_die_bus_width;
uint32_t each_die_6gb_or_12gb;
};
struct rk3399_sdram_config {
struct rk3399_sdram_channel_config ch[2];
uint32_t dramtype;
uint32_t channal_num;
};
struct rk3399_sdram_default_config {
unsigned char bl;
/* 1:auto precharge, 0:never auto precharge */
unsigned char ap;
/* dram driver strength */
unsigned char dramds;
/* dram ODT, if odt=0, this parameter invalid */
unsigned char dramodt;
/* ca ODT, if odt=0, this parameter invalid
* only used by LPDDR4
*/
unsigned char caodt;
unsigned char burst_ref_cnt;
/* zqcs period, unit(s) */
unsigned char zqcsi;
};
struct ddr_dts_config_timing {
unsigned int ddr3_speed_bin;
unsigned int pd_idle;
unsigned int sr_idle;
unsigned int sr_mc_gate_idle;
unsigned int srpd_lite_idle;
unsigned int standby_idle;
unsigned int auto_pd_dis_freq;
unsigned int ddr3_dll_dis_freq;
unsigned int phy_dll_dis_freq;
unsigned int ddr3_odt_dis_freq;
unsigned int ddr3_drv;
unsigned int ddr3_odt;
unsigned int phy_ddr3_ca_drv;
unsigned int phy_ddr3_dq_drv;
unsigned int phy_ddr3_odt;
unsigned int lpddr3_odt_dis_freq;
unsigned int lpddr3_drv;
unsigned int lpddr3_odt;
unsigned int phy_lpddr3_ca_drv;
unsigned int phy_lpddr3_dq_drv;
unsigned int phy_lpddr3_odt;
unsigned int lpddr4_odt_dis_freq;
unsigned int lpddr4_drv;
unsigned int lpddr4_dq_odt;
unsigned int lpddr4_ca_odt;
unsigned int phy_lpddr4_ca_drv;
unsigned int phy_lpddr4_ck_cs_drv;
unsigned int phy_lpddr4_dq_drv;
unsigned int phy_lpddr4_odt;
uint32_t available;
};
struct drv_odt_lp_config {
uint32_t ddr3_speed_bin;
uint32_t pd_idle;
uint32_t sr_idle;
uint32_t sr_mc_gate_idle;
uint32_t srpd_lite_idle;
uint32_t standby_idle;
uint32_t ddr3_dll_dis_freq;/* for ddr3 only */
uint32_t phy_dll_dis_freq;
uint32_t odt_dis_freq;
uint32_t dram_side_drv;
uint32_t dram_side_dq_odt;
uint32_t dram_side_ca_odt;
uint32_t phy_side_ca_drv;
uint32_t phy_side_ck_cs_drv;
uint32_t phy_side_dq_drv;
uint32_t phy_side_odt;
};
#define KHz (1000)
#define MHz (1000*KHz)
#define GHz (1000*MHz)
#define PI_CA_TRAINING (1 << 0)
#define PI_WRITE_LEVELING (1 << 1)
#define PI_READ_GATE_TRAINING (1 << 2)
#define PI_READ_LEVELING (1 << 3)
#define PI_WDQ_LEVELING (1 << 4)
#define PI_FULL_TARINING (0xff)
#define READ_CH_CNT(val) (1+((val>>12)&0x1))
#define READ_CH_INFO(val) ((val>>28)&0x3)
/* row_3_4:0=normal, 1=6Gb or 12Gb */
#define READ_CH_ROW_INFO(val, ch) ((val>>(30+(ch)))&0x1)
#define READ_DRAMTYPE_INFO(val) ((val>>13)&0x7)
#define READ_CS_INFO(val, ch) ((((val)>>(11+(ch)*16))&0x1)+1)
#define READ_BW_INFO(val, ch) (2>>(((val)>>(2+(ch)*16))&0x3))
#define READ_COL_INFO(val, ch) (9+(((val)>>(9+(ch)*16))&0x3))
#define READ_BK_INFO(val, ch) (3-(((val)>>(8+(ch)*16))&0x1))
#define READ_CS0_ROW_INFO(val, ch) (13+(((val)>>(6+(ch)*16))&0x3))
#define READ_CS1_ROW_INFO(val, ch) (13+(((val)>>(4+(ch)*16))&0x3))
#define READ_DIE_BW_INFO(val, ch) (2>>((val>>((ch)*16))&0x3))
#define __sramdata __attribute__((section(".sram.data")))
#define __sramconst __attribute__((section(".sram.rodata")))
#define __sramlocalfunc __attribute__((section(".sram.text")))
#define __sramfunc __attribute__((section(".sram.text"))) \
__attribute__((noinline))
#define DDR_SAVE_SP(save_sp) (save_sp = ddr_save_sp(((uint32_t)\
(SRAM_CODE_BASE + 0x2000) & (~7))))
#define DDR_RESTORE_SP(save_sp) ddr_save_sp(save_sp)
void ddr_init(void);
uint64_t ddr_set_rate(uint64_t hz);
uint64_t ddr_round_rate(uint64_t hz);
uint64_t ddr_get_rate(void);
void clr_dcf_irq(void);
uint64_t dts_timing_receive(uint64_t timing, uint64_t index);
#endif

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plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c Normal file
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/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _DRAM_SPEC_TIMING_HEAD_
#define _DRAM_SPEC_TIMING_HEAD_
#include <stdint.h>
enum {
DDR3 = 3,
LPDDR2 = 5,
LPDDR3 = 6,
LPDDR4 = 7,
UNUSED = 0xFF
};
enum ddr3_speed_rate {
/* 5-5-5 */
DDR3_800D = 0,
/* 6-6-6 */
DDR3_800E = 1,
/* 6-6-6 */
DDR3_1066E = 2,
/* 7-7-7 */
DDR3_1066F = 3,
/* 8-8-8 */
DDR3_1066G = 4,
/* 7-7-7 */
DDR3_1333F = 5,
/* 8-8-8 */
DDR3_1333G = 6,
/* 9-9-9 */
DDR3_1333H = 7,
/* 10-10-10 */
DDR3_1333J = 8,
/* 8-8-8 */
DDR3_1600G = 9,
/* 9-9-9 */
DDR3_1600H = 10,
/* 10-10-10 */
DDR3_1600J = 11,
/* 11-11-11 */
DDR3_1600K = 12,
/* 10-10-10 */
DDR3_1866J = 13,
/* 11-11-11 */
DDR3_1866K = 14,
/* 12-12-12 */
DDR3_1866L = 15,
/* 13-13-13 */
DDR3_1866M = 16,
/* 11-11-11 */
DDR3_2133K = 17,
/* 12-12-12 */
DDR3_2133L = 18,
/* 13-13-13 */
DDR3_2133M = 19,
/* 14-14-14 */
DDR3_2133N = 20,
DDR3_DEFAULT = 21,
};
#define max(a, b) (((a) > (b)) ? (a) : (b))
#define range(mi, val, ma) (((ma) > (val)) ? (max(mi, val)) : (ma))
struct dram_timing_t {
/* unit MHz */
uint32_t mhz;
/* some timing unit is us */
uint32_t tinit1;
uint32_t tinit2;
uint32_t tinit3;
uint32_t tinit4;
uint32_t tinit5;
/* reset low, DDR3:200us */
uint32_t trstl;
/* reset high to CKE high, DDR3:500us */
uint32_t trsth;
uint32_t trefi;
/* base */
uint32_t trcd;
/* trp per bank */
uint32_t trppb;
/* trp all bank */
uint32_t trp;
uint32_t twr;
uint32_t tdal;
uint32_t trtp;
uint32_t trc;
uint32_t trrd;
uint32_t tccd;
uint32_t twtr;
uint32_t trtw;
uint32_t tras_max;
uint32_t tras_min;
uint32_t tfaw;
uint32_t trfc;
uint32_t tdqsck;
uint32_t tdqsck_max;
/* pd or sr */
uint32_t txsr;
uint32_t txsnr;
uint32_t txp;
uint32_t txpdll;
uint32_t tdllk;
uint32_t tcke;
uint32_t tckesr;
uint32_t tcksre;
uint32_t tcksrx;
uint32_t tdpd;
/* mode regiter timing */
uint32_t tmod;
uint32_t tmrd;
uint32_t tmrr;
uint32_t tmrri;
/* ODT */
uint32_t todton;
/* ZQ */
uint32_t tzqinit;
uint32_t tzqcs;
uint32_t tzqoper;
uint32_t tzqreset;
/* Write Leveling */
uint32_t twlmrd;
uint32_t twlo;
uint32_t twldqsen;
/* CA Training */
uint32_t tcackel;
uint32_t tcaent;
uint32_t tcamrd;
uint32_t tcackeh;
uint32_t tcaext;
uint32_t tadr;
uint32_t tmrz;
uint32_t tcacd;
/* mode register */
uint32_t mr[4];
uint32_t mr11;
/* lpddr4 spec */
uint32_t mr12;
uint32_t mr13;
uint32_t mr14;
uint32_t mr16;
uint32_t mr17;
uint32_t mr20;
uint32_t mr22;
uint32_t tccdmw;
uint32_t tppd;
uint32_t tescke;
uint32_t tsr;
uint32_t tcmdcke;
uint32_t tcscke;
uint32_t tckelcs;
uint32_t tcsckeh;
uint32_t tckehcs;
uint32_t tmrwckel;
uint32_t tzqcal;
uint32_t tzqlat;
uint32_t tzqcke;
uint32_t tvref_long;
uint32_t tvref_short;
uint32_t tvrcg_enable;
uint32_t tvrcg_disable;
uint32_t tfc_long;
uint32_t tckfspe;
uint32_t tckfspx;
uint32_t tckehcmd;
uint32_t tckelcmd;
uint32_t tckelpd;
uint32_t tckckel;
/* other */
uint32_t al;
uint32_t cl;
uint32_t cwl;
uint32_t bl;
};
struct dram_info_t {
/* speed_rate only used when DDR3 */
enum ddr3_speed_rate speed_rate;
/* 1: use CS0, 2: use CS0 and CS1 */
uint32_t cs_cnt;
/* give the max per-die capability on each rank/cs */
uint32_t per_die_capability[2];
};
struct timing_related_config {
struct dram_info_t dram_info[2];
uint32_t dram_type;
/* MHz */
uint32_t freq;
uint32_t ch_cnt;
uint32_t bl;
/* 1:auto precharge, 0:never auto precharge */
uint32_t ap;
/*
* 1:dll bypass, 0:dll normal
* dram and controller dll bypass at the same time
*/
uint32_t dllbp;
/* 1:odt enable, 0:odt disable */
uint32_t odt;
/* 1:enable, 0:disabe */
uint32_t rdbi;
uint32_t wdbi;
/* dram driver strength */
uint32_t dramds;
/* dram ODT, if odt=0, this parameter invalid */
uint32_t dramodt;
/*
* ca ODT, if odt=0, this parameter invalid
* it only used by LPDDR4
*/
uint32_t caodt;
};
/* mr0 for ddr3 */
#define DDR3_BL8 (0)
#define DDR3_BC4_8 (1)
#define DDR3_BC4 (2)
#define DDR3_CL(n) (((((n) - 4) & 0x7) << 4)\
| ((((n) - 4) & 0x8) >> 1))
#define DDR3_WR(n) (((n) & 0x7) << 9)
#define DDR3_DLL_RESET (1 << 8)
#define DDR3_DLL_DERESET (0 << 8)
/* mr1 for ddr3 */
#define DDR3_DLL_ENABLE (0)
#define DDR3_DLL_DISABLE (1)
#define DDR3_MR1_AL(n) (((n) & 0x3) << 3)
#define DDR3_DS_40 (0)
#define DDR3_DS_34 (1 << 1)
#define DDR3_RTT_NOM_DIS (0)
#define DDR3_RTT_NOM_60 (1 << 2)
#define DDR3_RTT_NOM_120 (1 << 6)
#define DDR3_RTT_NOM_40 ((1 << 2) | (1 << 6))
#define DDR3_TDQS (1 << 11)
/* mr2 for ddr3 */
#define DDR3_MR2_CWL(n) ((((n) - 5) & 0x7) << 3)
#define DDR3_RTT_WR_DIS (0)
#define DDR3_RTT_WR_60 (1 << 9)
#define DDR3_RTT_WR_120 (2 << 9)
/*
* MR0 (Device Information)
* 0:DAI complete, 1:DAI still in progress
*/
#define LPDDR2_DAI (0x1)
/* 0:S2 or S4 SDRAM, 1:NVM */
#define LPDDR2_DI (0x1 << 1)
/* 0:DNV not supported, 1:DNV supported */
#define LPDDR2_DNVI (0x1 << 2)
#define LPDDR2_RZQI (0x3 << 3)
/*
* 00:RZQ self test not supported,
* 01:ZQ-pin may connect to VDDCA or float
* 10:ZQ-pin may short to GND.
* 11:ZQ-pin self test completed, no error condition detected.
*/
/* MR1 (Device Feature) */
#define LPDDR2_BL4 (0x2)
#define LPDDR2_BL8 (0x3)
#define LPDDR2_BL16 (0x4)
#define LPDDR2_N_WR(n) (((n) - 2) << 5)
/* MR2 (Device Feature 2) */
#define LPDDR2_RL3_WL1 (0x1)
#define LPDDR2_RL4_WL2 (0x2)
#define LPDDR2_RL5_WL2 (0x3)
#define LPDDR2_RL6_WL3 (0x4)
#define LPDDR2_RL7_WL4 (0x5)
#define LPDDR2_RL8_WL4 (0x6)
/* MR3 (IO Configuration 1) */
#define LPDDR2_DS_34 (0x1)
#define LPDDR2_DS_40 (0x2)
#define LPDDR2_DS_48 (0x3)
#define LPDDR2_DS_60 (0x4)
#define LPDDR2_DS_80 (0x6)
/* optional */
#define LPDDR2_DS_120 (0x7)
/* MR4 (Device Temperature) */
#define LPDDR2_TREF_MASK (0x7)
#define LPDDR2_4_TREF (0x1)
#define LPDDR2_2_TREF (0x2)
#define LPDDR2_1_TREF (0x3)
#define LPDDR2_025_TREF (0x5)
#define LPDDR2_025_TREF_DERATE (0x6)
#define LPDDR2_TUF (0x1 << 7)
/* MR8 (Basic configuration 4) */
#define LPDDR2_S4 (0x0)
#define LPDDR2_S2 (0x1)
#define LPDDR2_N (0x2)
/* Unit:MB */
#define LPDDR2_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf))
#define LPDDR2_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3))
/* MR10 (Calibration) */
#define LPDDR2_ZQINIT (0xff)
#define LPDDR2_ZQCL (0xab)
#define LPDDR2_ZQCS (0x56)
#define LPDDR2_ZQRESET (0xc3)
/* MR16 (PASR Bank Mask), S2 SDRAM Only */
#define LPDDR2_PASR_FULL (0x0)
#define LPDDR2_PASR_1_2 (0x1)
#define LPDDR2_PASR_1_4 (0x2)
#define LPDDR2_PASR_1_8 (0x3)
/*
* MR0 (Device Information)
* 0:DAI complete,
* 1:DAI still in progress
*/
#define LPDDR3_DAI (0x1)
/*
* 00:RZQ self test not supported,
* 01:ZQ-pin may connect to VDDCA or float
* 10:ZQ-pin may short to GND.
* 11:ZQ-pin self test completed, no error condition detected.
*/
#define LPDDR3_RZQI (0x3 << 3)
/*
* 0:DRAM does not support WL(Set B),
* 1:DRAM support WL(Set B)
*/
#define LPDDR3_WL_SUPOT (1 << 6)
/*
* 0:DRAM does not support RL=3,nWR=3,WL=1;
* 1:DRAM supports RL=3,nWR=3,WL=1 for frequencies <=166
*/
#define LPDDR3_RL3_SUPOT (1 << 7)
/* MR1 (Device Feature) */
#define LPDDR3_BL8 (0x3)
#define LPDDR3_N_WR(n) ((n) << 5)
/* MR2 (Device Feature 2), WL Set A,default */
/* <=166MHz,optional*/
#define LPDDR3_RL3_WL1 (0x1)
/* <=400MHz*/
#define LPDDR3_RL6_WL3 (0x4)
/* <=533MHz*/
#define LPDDR3_RL8_WL4 (0x6)
/* <=600MHz*/
#define LPDDR3_RL9_WL5 (0x7)
/* <=667MHz,default*/
#define LPDDR3_RL10_WL6 (0x8)
/* <=733MHz*/
#define LPDDR3_RL11_WL6 (0x9)
/* <=800MHz*/
#define LPDDR3_RL12_WL6 (0xa)
/* <=933MHz*/
#define LPDDR3_RL14_WL8 (0xc)
/* <=1066MHz*/
#define LPDDR3_RL16_WL8 (0xe)
/* WL Set B, optional */
/* <=667MHz,default*/
#define LPDDR3_RL10_WL8 (0x8)
/* <=733MHz*/
#define LPDDR3_RL11_WL9 (0x9)
/* <=800MHz*/
#define LPDDR3_RL12_WL9 (0xa)
/* <=933MHz*/
#define LPDDR3_RL14_WL11 (0xc)
/* <=1066MHz*/
#define LPDDR3_RL16_WL13 (0xe)
/* 1:enable nWR programming > 9(default)*/
#define LPDDR3_N_WRE (1 << 4)
/* 1:Select WL Set B*/
#define LPDDR3_WL_S (1 << 6)
/* 1:enable*/
#define LPDDR3_WR_LEVEL (1 << 7)
/* MR3 (IO Configuration 1) */
#define LPDDR3_DS_34 (0x1)
#define LPDDR3_DS_40 (0x2)
#define LPDDR3_DS_48 (0x3)
#define LPDDR3_DS_60 (0x4)
#define LPDDR3_DS_80 (0x6)
#define LPDDR3_DS_34D_40U (0x9)
#define LPDDR3_DS_40D_48U (0xa)
#define LPDDR3_DS_34D_48U (0xb)
/* MR4 (Device Temperature) */
#define LPDDR3_TREF_MASK (0x7)
/* SDRAM Low temperature operating limit exceeded */
#define LPDDR3_LT_EXED (0x0)
#define LPDDR3_4_TREF (0x1)
#define LPDDR3_2_TREF (0x2)
#define LPDDR3_1_TREF (0x3)
#define LPDDR3_05_TREF (0x4)
#define LPDDR3_025_TREF (0x5)
#define LPDDR3_025_TREF_DERATE (0x6)
/* SDRAM High temperature operating limit exceeded */
#define LPDDR3_HT_EXED (0x7)
/* 1:value has changed since last read of MR4 */
#define LPDDR3_TUF (0x1 << 7)
/* MR8 (Basic configuration 4) */
#define LPDDR3_S8 (0x3)
#define LPDDR3_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf))
#define LPDDR3_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3))
/* MR10 (Calibration) */
#define LPDDR3_ZQINIT (0xff)
#define LPDDR3_ZQCL (0xab)
#define LPDDR3_ZQCS (0x56)
#define LPDDR3_ZQRESET (0xc3)
/* MR11 (ODT Control) */
#define LPDDR3_ODT_60 (1)
#define LPDDR3_ODT_120 (2)
#define LPDDR3_ODT_240 (3)
#define LPDDR3_ODT_DIS (0)
/* MR2 (Device Feature 2) */
/* RL & nRTP for DBI-RD Disabled */
#define LPDDR4_RL6_NRTP8 (0x0)
#define LPDDR4_RL10_NRTP8 (0x1)
#define LPDDR4_RL14_NRTP8 (0x2)
#define LPDDR4_RL20_NRTP8 (0x3)
#define LPDDR4_RL24_NRTP10 (0x4)
#define LPDDR4_RL28_NRTP12 (0x5)
#define LPDDR4_RL32_NRTP14 (0x6)
#define LPDDR4_RL36_NRTP16 (0x7)
/* RL & nRTP for DBI-RD Disabled */
#define LPDDR4_RL12_NRTP8 (0x1)
#define LPDDR4_RL16_NRTP8 (0x2)
#define LPDDR4_RL22_NRTP8 (0x3)
#define LPDDR4_RL28_NRTP10 (0x4)
#define LPDDR4_RL32_NRTP12 (0x5)
#define LPDDR4_RL36_NRTP14 (0x6)
#define LPDDR4_RL40_NRTP16 (0x7)
/* WL Set A,default */
#define LPDDR4_A_WL4 (0x0)
#define LPDDR4_A_WL6 (0x1)
#define LPDDR4_A_WL8 (0x2)
#define LPDDR4_A_WL10 (0x3)
#define LPDDR4_A_WL12 (0x4)
#define LPDDR4_A_WL14 (0x5)
#define LPDDR4_A_WL16 (0x6)
#define LPDDR4_A_WL18 (0x7)
/* WL Set B, optional */
#define LPDDR4_B_WL4 (0x0 << 3)
#define LPDDR4_B_WL8 (0x1 << 3)
#define LPDDR4_B_WL12 (0x2 << 3)
#define LPDDR4_B_WL18 (0x3 << 3)
#define LPDDR4_B_WL22 (0x4 << 3)
#define LPDDR4_B_WL26 (0x5 << 3)
#define LPDDR4_B_WL30 (0x6 << 3)
#define LPDDR4_B_WL34 (0x7 << 3)
/* 1:Select WL Set B*/
#define LPDDR4_WL_B (1 << 6)
/* 1:enable*/
#define LPDDR4_WR_LEVEL (1 << 7)
/* MR3 */
#define LPDDR4_VDDQ_2_5 (0)
#define LPDDR4_VDDQ_3 (1)
#define LPDDR4_WRPST_0_5_TCK (0 << 1)
#define LPDDR4_WRPST_1_5_TCK (1 << 1)
#define LPDDR4_PPR_EN (1 << 2)
/* PDDS */
#define LPDDR4_PDDS_240 (0x1 << 3)
#define LPDDR4_PDDS_120 (0x2 << 3)
#define LPDDR4_PDDS_80 (0x3 << 3)
#define LPDDR4_PDDS_60 (0x4 << 3)
#define LPDDR4_PDDS_48 (0x5 << 3)
#define LPDDR4_PDDS_40 (0x6 << 3)
#define LPDDR4_DBI_RD_EN (1 << 6)
#define LPDDR4_DBI_WR_EN (1 << 7)
/* MR11 (ODT Control) */
#define LPDDR4_DQODT_240 (1)
#define LPDDR4_DQODT_120 (2)
#define LPDDR4_DQODT_80 (3)
#define LPDDR4_DQODT_60 (4)
#define LPDDR4_DQODT_48 (5)
#define LPDDR4_DQODT_40 (6)
#define LPDDR4_DQODT_DIS (0)
#define LPDDR4_CAODT_240 (1 << 4)
#define LPDDR4_CAODT_120 (2 << 4)
#define LPDDR4_CAODT_80 (3 << 4)
#define LPDDR4_CAODT_60 (4 << 4)
#define LPDDR4_CAODT_48 (5 << 4)
#define LPDDR4_CAODT_40 (6 << 4)
#define LPDDR4_CAODT_DIS (0 << 4)
/*
* Description: depend on input parameter "timing_config",
* and calculate correspond "dram_type"
* spec timing to "pdram_timing"
* parameters:
* input: timing_config
* output: pdram_timing
* NOTE: MR ODT is set, need to disable by controller
*/
void dram_get_parameter(struct timing_related_config *timing_config,
struct dram_timing_t *pdram_timing);
#endif /* _DRAM_SPEC_TIMING_HEAD_ */

37
plat/rockchip/rk3399/drivers/soc/soc.h
View File

@ -48,6 +48,12 @@
#define NO_PLL_BYPASS (0x00)
#define NO_PLL_PWRDN (0x00)
#define FBDIV(n) ((0xfff << 16) | n)
#define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12))
#define POSTDIV1(n) ((0x7 << (8 + 16)) | (n << 8))
#define REFDIV(n) ((0x3F << 16) | n)
#define PLL_LOCK(n) ((n >> 31) & 0x1)
#define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\
PLL_MODE_MSK, PLL_MODE_SHIFT)
@ -107,6 +113,31 @@ struct deepsleep_data_s {
uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT];
};
/**************************************************
* pmugrf reg, offset
**************************************************/
#define PMUGRF_OSREG(n) (0x300 + (n) * 4)
/**************************************************
* DCF reg, offset
**************************************************/
#define DCF_DCF_CTRL 0x0
#define DCF_DCF_ADDR 0x8
#define DCF_DCF_ISR 0xc
#define DCF_DCF_TOSET 0x14
#define DCF_DCF_TOCMD 0x18
#define DCF_DCF_CMD_CFG 0x1c
/* DCF_DCF_ISR */
#define DCF_TIMEOUT (1 << 2)
#define DCF_ERR (1 << 1)
#define DCF_DONE (1 << 0)
/* DCF_DCF_CTRL */
#define DCF_VOP_HW_EN (1 << 2)
#define DCF_STOP (1 << 1)
#define DCF_START (1 << 0)
#define CYCL_24M_CNT_US(us) (24 * us)
#define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000))
#define CYCL_32K_CNT_MS(ms) (ms * 32)
@ -256,6 +287,12 @@ struct deepsleep_data_s {
#define PWM_DISABLE (0 << 0)
#define PWM_ENABLE (1 << 0)
/* grf reg offset */
#define GRF_DDRC0_CON0 0xe380
#define GRF_DDRC0_CON1 0xe384
#define GRF_DDRC1_CON0 0xe388
#define GRF_DDRC1_CON1 0xe38c
/*
* When system reset in running state, we want the cpus to be reboot
* from maskrom (system reboot),

38
plat/rockchip/rk3399/plat_sip_calls.c
View File

@ -29,6 +29,42 @@
#include <plat_sip_calls.h>
#include <rockchip_sip_svc.h>
#include <runtime_svc.h>
#include <dram.h>
#define RK_SIP_DDR_CFG64 0x82000008
#define CONFIG_DRAM_INIT 0x00
#define CONFIG_DRAM_SET_RATE 0x01
#define CONFIG_DRAM_ROUND_RATE 0x02
#define CONFIG_DRAM_SET_AT_SR 0x03
#define CONFIG_DRAM_GET_BW 0x04
#define CONFIG_DRAM_GET_RATE 0x05
#define CONFIG_DRAM_CLR_IRQ 0x06
#define CONFIG_DRAM_SET_PARAM 0x07
uint64_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, uint64_t id)
{
switch (id) {
case CONFIG_DRAM_INIT:
ddr_init();
break;
case CONFIG_DRAM_SET_RATE:
return ddr_set_rate(arg0);
case CONFIG_DRAM_ROUND_RATE:
return ddr_round_rate(arg0);
case CONFIG_DRAM_GET_RATE:
return ddr_get_rate();
case CONFIG_DRAM_CLR_IRQ:
clr_dcf_irq();
break;
case CONFIG_DRAM_SET_PARAM:
dts_timing_receive(arg0, arg1);
break;
default:
break;
}
return 0;
}
uint64_t rockchip_plat_sip_handler(uint32_t smc_fid,
uint64_t x1,
@ -40,6 +76,8 @@ uint64_t rockchip_plat_sip_handler(uint32_t smc_fid,
uint64_t flags)
{
switch (smc_fid) {
case RK_SIP_DDR_CFG64:
SMC_RET1(handle, ddr_smc_handler(x1, x2, x3));
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
SMC_RET1(handle, SMC_UNK);

5
plat/rockchip/rk3399/platform.mk
View File

@ -40,6 +40,7 @@ PLAT_INCLUDES := -I${RK_PLAT_COMMON}/ \
-I${RK_PLAT_SOC}/drivers/pmu/ \
-I${RK_PLAT_SOC}/drivers/pwm/ \
-I${RK_PLAT_SOC}/drivers/soc/ \
-I${RK_PLAT_SOC}/drivers/dram/ \
-I${RK_PLAT_SOC}/include/ \
RK_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
@ -76,6 +77,8 @@ BL31_SOURCES += ${RK_GIC_SOURCES}
${RK_PLAT_SOC}/drivers/gpio/rk3399_gpio.c \
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
${RK_PLAT_SOC}/drivers/pwm/pwm.c \
${RK_PLAT_SOC}/drivers/soc/soc.c
${RK_PLAT_SOC}/drivers/soc/soc.c \
${RK_PLAT_SOC}/drivers/dram/dram.c \
${RK_PLAT_SOC}/drivers/dram/dram_spec_timing.c
ENABLE_PLAT_COMPAT := 0

23
plat/rockchip/rk3399/rk3399_def.h
View File

@ -61,6 +61,12 @@
#define PWM_BASE (MMIO_BASE + 0x1420000)
#define PWM_SIZE SIZE_K(64)
#define CIC_BASE (MMIO_BASE + 0x1620000)
#define CIC_SIZE SIZE_K(4)
#define DCF_BASE (MMIO_BASE + 0x16a0000)
#define DCF_SIZE SIZE_K(4)
#define GPIO0_BASE (MMIO_BASE + 0x1720000)
#define GPIO0_SIZE SIZE_K(64)
@ -85,12 +91,21 @@
#define STIME_BASE (MMIO_BASE + 0x1860000)
#define STIME_SIZE SIZE_K(64)
#define SRAM_BASE (MMIO_BASE + 0x18c0000)
#define SRAM_SIZE SIZE_K(192)
#define SERVICE_NOC_0_BASE (MMIO_BASE + 0x1a50000)
#define NOC_0_SIZE SIZE_K(192)
#define DDRC0_BASE (MMIO_BASE + 0x1a80000)
#define DDRC0_SIZE SIZE_K(32)
#define SERVICE_NOC_1_BASE (MMIO_BASE + 0x1a84000)
#define NOC_1_SIZE SIZE_K(16)
#define DDRC1_BASE (MMIO_BASE + 0x1a88000)
#define DDRC1_SIZE SIZE_K(32)
#define SERVICE_NOC_2_BASE (MMIO_BASE + 0x1a8c000)
#define NOC_2_SIZE SIZE_K(16)
@ -100,6 +115,14 @@
#define CCI500_BASE (MMIO_BASE + 0x1b00000)
#define CCI500_SIZE SIZE_M(1)
#define DDR_PI_OFFSET 0x800
#define DDR_PHY_OFFSET 0x2000
#define DDRC0_PI_BASE (DDRC0_BASE + DDR_PI_OFFSET)
#define DDRC0_PHY_BASE (DDRC0_BASE + DDR_PHY_OFFSET)
#define DDRC1_PI_BASE (DDRC1_BASE + DDR_PI_OFFSET)
#define DDRC1_PHY_BASE (DDRC1_BASE + DDR_PHY_OFFSET)
/* Aggregate of all devices in the first GB */
#define RK3399_DEV_RNG0_BASE MMIO_BASE
#define RK3399_DEV_RNG0_SIZE 0x1d00000