SSBS: init SPSR register with default SSBS value
This patch introduces an additional precautionary step to further enhance protection against variant 4. During the context initialisation before we enter the various BL stages, the SPSR.SSBS bit is explicitly set to zero. As such, speculative loads/stores are by default disabled for all BL stages when they start executing. Subsequently, each BL stage, can choose to enable speculative loads/stores or keep them disabled. This change doesn't affect the initial execution context of BL33 which is totally platform dependent and, thus, it is intentionally left up to each platform to initialise. For Arm platforms, SPSR.SSBS is set to zero for BL33 too. This means that, for Arm platforms, all BL stages start with speculative loads/stores disabled. Change-Id: Ie47d39c391d3f20fc2852fc59dbd336f8cacdd6c Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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@ -294,6 +294,8 @@
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#define SPSR_MODE_SHIFT U(0)
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#define SPSR_MODE_MASK U(0x7)
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#define SPSR_SSBS_BIT BIT_32(23)
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#define DISABLE_ALL_EXCEPTIONS \
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(SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
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@ -384,11 +386,12 @@
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#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
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#define SPSR_MODE32(mode, isa, endian, aif) \
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(MODE_RW_32 << MODE_RW_SHIFT | \
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((MODE_RW_32 << MODE_RW_SHIFT | \
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((mode) & MODE32_MASK) << MODE32_SHIFT | \
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((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
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((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
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((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
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((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) & \
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(~(SPSR_SSBS_BIT)))
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/*
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* TTBR definitions
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@ -411,6 +411,9 @@
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#define SPSR_M_AARCH64 U(0x0)
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#define SPSR_M_AARCH32 U(0x1)
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#define SPSR_SSBS_BIT_AARCH64 BIT_64(12)
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#define SPSR_SSBS_BIT_AARCH32 BIT_64(23)
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#define DISABLE_ALL_EXCEPTIONS \
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(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
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@ -535,18 +538,20 @@
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#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
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#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
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#define SPSR_64(el, sp, daif) \
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((MODE_RW_64 << MODE_RW_SHIFT) | \
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(((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \
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(((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \
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(((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT))
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#define SPSR_64(el, sp, daif) \
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(((MODE_RW_64 << MODE_RW_SHIFT) | \
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(((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \
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(((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \
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(((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \
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(~(SPSR_SSBS_BIT_AARCH64)))
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#define SPSR_MODE32(mode, isa, endian, aif) \
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((MODE_RW_32 << MODE_RW_SHIFT) | \
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(((MODE_RW_32 << MODE_RW_SHIFT) | \
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(((mode) & MODE32_MASK) << MODE32_SHIFT) | \
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(((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
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(((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
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(((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT))
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(((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \
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(~(SPSR_SSBS_BIT_AARCH32)))
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/*
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* TTBR Definitions
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