From c2d18ca80f4bd32f58ba07f53d9bb2586df18fc0 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Mon, 26 Oct 2020 15:21:25 +0100 Subject: [PATCH] fix(plat/st): correct IO compensation disabling In stm32mp1_syscfg_disable_io_compensation(), to disable the IO compensation cell, we have to set the corresponding bit in SYSCFG_CMPENCLRR register, instead of clearing the bit in SETR register. Change-Id: I510a50451f8afb9e98c24e1ea84efbf73a39e6b4 Signed-off-by: Yann Gautier --- plat/st/stm32mp1/stm32mp1_syscfg.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/plat/st/stm32mp1/stm32mp1_syscfg.c b/plat/st/stm32mp1/stm32mp1_syscfg.c index 109725c8a..793ad714a 100644 --- a/plat/st/stm32mp1/stm32mp1_syscfg.c +++ b/plat/st/stm32mp1/stm32mp1_syscfg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,6 +22,7 @@ #define SYSCFG_ICNR 0x1CU #define SYSCFG_CMPCR 0x20U #define SYSCFG_CMPENSETR 0x24U +#define SYSCFG_CMPENCLRR 0x28U /* * SYSCFG_BOOTR Register @@ -167,8 +168,7 @@ void stm32mp1_syscfg_disable_io_compensation(void) mmio_write_32(SYSCFG_BASE + SYSCFG_CMPCR, value | SYSCFG_CMPCR_SW_CTRL); - mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPENSETR, - SYSCFG_CMPENSETR_MPU_EN); + mmio_setbits_32(SYSCFG_BASE + SYSCFG_CMPENCLRR, SYSCFG_CMPENSETR_MPU_EN); stm32mp1_clk_disable_non_secure(SYSCFG); }