Merge "fix(errata): workaround for Cortex X2 erratum 2083908" into integration
This commit is contained in:
Bipin Ravi
TrustedFirmware Code Review
commit
c2d75fa7a3
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@ -441,6 +441,11 @@ For Neoverse N2, the following errata build flags are defined :
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- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2
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CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
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For Cortex-X2, the following errata build flags are defined :
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- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2
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CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open.
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DSU Errata Workarounds
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----------------------
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@ -20,4 +20,9 @@
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#define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary Control Register 5 definitions
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******************************************************************************/
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#define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0
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#endif /* CORTEX_X2_H */
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@ -21,6 +21,35 @@
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#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Cortex X2 Errata #2083908.
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* This applies to revision r2p0 and is open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x2, x17
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* --------------------------------------------------
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*/
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func errata_cortex_x2_2083908_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2083908
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cbz x0, 1f
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/* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */
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mrs x1, CORTEX_X2_CPUACTLR5_EL1
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orr x1, x1, #BIT(13)
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msr CORTEX_X2_CPUACTLR5_EL1, x1
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1:
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ret x17
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endfunc errata_cortex_x2_2083908_wa
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func check_errata_2083908
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/* Applies to r2p0 */
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mov x1, #0x20
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mov x2, #0x20
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b cpu_rev_var_range
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endfunc check_errata_2083908
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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@ -42,15 +71,39 @@ endfunc cortex_x2_core_pwr_dwn
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*/
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#if REPORT_ERRATA
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func cortex_x2_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_X2_2083908, cortex_x2, 2083908
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_x2_errata_report
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#endif
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func cortex_x2_reset_func
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mov x19, x30
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/* Disable speculative loads */
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msr SSBS, xzr
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isb
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ret
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/* Get the CPU revision and stash it in x18. */
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_X2_2083908
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mov x0, x18
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bl errata_cortex_x2_2083908_wa
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#endif
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ret x19
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endfunc cortex_x2_reset_func
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/* ---------------------------------------------
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@ -495,6 +495,10 @@ ERRATA_A710_2055002 ?=0
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# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
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ERRATA_A710_2017096 ?=0
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# Flag to apply erratum 2083908 workaround during reset. This erratum applies
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# to revision r2p0 of the Cortex-X2 cpu and is still open.
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ERRATA_X2_2083908 ?=0
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# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
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# Applying the workaround results in higher DSU power consumption on idle.
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ERRATA_DSU_798953 ?=0
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@ -920,6 +924,10 @@ $(eval $(call add_define,ERRATA_A710_2055002))
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$(eval $(call assert_boolean,ERRATA_A710_2017096))
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$(eval $(call add_define,ERRATA_A710_2017096))
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# Process ERRATA_X2_2083908 flag
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$(eval $(call assert_boolean,ERRATA_X2_2083908))
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$(eval $(call add_define,ERRATA_X2_2083908))
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# Process ERRATA_DSU_798953 flag
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$(eval $(call assert_boolean,ERRATA_DSU_798953))
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$(eval $(call add_define,ERRATA_DSU_798953))
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@ -142,7 +142,8 @@ else
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lib/cpus/aarch64/cortex_a65ae.S \
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lib/cpus/aarch64/cortex_a78c.S \
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lib/cpus/aarch64/cortex_hayes.S \
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lib/cpus/aarch64/cortex_hunter.S
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lib/cpus/aarch64/cortex_hunter.S \
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lib/cpus/aarch64/cortex_x2.S
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endif
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# AArch64/AArch32 cores
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FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
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