Merge pull request #1458 from Andre-ARM/allwinner/fixes
allwinner: various smaller fixes
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commit
c2f27cedb3
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@ -4,9 +4,11 @@ Trusted Firmware-A for Allwinner ARMv8 SoCs
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Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Allwinner
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SoCs with ARMv8 cores. Only BL31 is used to provide proper EL3 setup and
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PSCI runtime services.
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U-Boot's SPL acts as a loader, loading both BL31 and BL33 (typically U-Boot).
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Loading is done from SD card, eMMC or SPI flash, also via an USB debug
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interface (FEL).
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BL31 lives in SRAM A2, which is documented to be accessible from secure
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world only.
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@ -20,6 +20,8 @@ Allwinner ARMv8 platform port
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-----------------------------
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:M: Andre Przywara <andre.przywara@arm.com>
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:G: `Andre-ARM`_
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:M: Samuel Holland <samuel@sholland.org>
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:G: `smaeul`_
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:F: docs/plat/allwinner.rst
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:F: plat/allwinner/
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@ -39,7 +39,7 @@
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
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PLATFORM_MAX_CPUS_PER_CLUSTER)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
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#define PLATFORM_MMAP_REGIONS 4
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#define PLATFORM_MMAP_REGIONS 3
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#define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT)
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#ifndef SPD_none
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@ -64,6 +64,22 @@ void bl31_plat_arch_setup(void)
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void bl31_platform_setup(void)
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{
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const char *soc_name;
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uint16_t soc_id = sunxi_read_soc_id();
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switch (soc_id) {
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case 0x1689:
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soc_name = "A64/H64/R18";
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break;
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case 0x1718:
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soc_name = "H5";
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break;
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default:
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soc_name = "unknown";
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break;
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}
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NOTICE("BL31: Detected Allwinner %s SoC (%04x)\n", soc_name, soc_id);
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generic_delay_timer_init();
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/* Configure the interrupt controller */
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@ -4,14 +4,15 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <mmio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <sunxi_def.h>
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#include <xlat_tables_v2.h>
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#include "sunxi_private.h"
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static mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = {
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MAP_REGION_FLAT(SUNXI_ROM_BASE, SUNXI_ROM_SIZE,
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MT_MEMORY | MT_RO | MT_SECURE),
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MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE,
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@ -54,3 +55,19 @@ void sunxi_configure_mmu_el3(int flags)
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enable_mmu_el3(0);
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}
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#define SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24)
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uint16_t sunxi_read_soc_id(void)
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{
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uint32_t reg = mmio_read_32(SRAM_VER_REG);
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/* Set bit 15 to prepare for the SOCID read. */
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mmio_write_32(SRAM_VER_REG, reg | BIT(15));
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reg = mmio_read_32(SRAM_VER_REG);
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/* deactivate the SOCID access again */
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mmio_write_32(SRAM_VER_REG, reg & ~BIT(15));
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return reg >> 16;
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}
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@ -18,7 +18,7 @@ static void sunxi_cpu_disable_power(unsigned int cluster, unsigned int core)
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if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0xff)
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return;
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INFO("PSCI: Disabling power to cluster %d core %d\n", cluster, core);
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VERBOSE("PSCI: Disabling power to cluster %d core %d\n", cluster, core);
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xff);
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}
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@ -28,7 +28,7 @@ static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core)
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if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0)
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return;
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INFO("PSCI: Enabling power to cluster %d core %d\n", cluster, core);
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VERBOSE("PSCI: Enabling power to cluster %d core %d\n", cluster, core);
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/* Power enable sequence from original Allwinner sources */
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xfe);
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@ -40,7 +40,7 @@ static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core)
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void sunxi_cpu_off(unsigned int cluster, unsigned int core)
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{
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INFO("PSCI: Powering off cluster %d core %d\n", cluster, core);
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VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core);
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/* Deassert DBGPWRDUP */
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mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
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@ -54,7 +54,7 @@ void sunxi_cpu_off(unsigned int cluster, unsigned int core)
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void sunxi_cpu_on(unsigned int cluster, unsigned int core)
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{
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INFO("PSCI: Powering on cluster %d core %d\n", cluster, core);
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VERBOSE("PSCI: Powering on cluster %d core %d\n", cluster, core);
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/* Assert CPU core reset */
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mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
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@ -76,8 +76,7 @@ static void __dead2 sunxi_system_reset(void)
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static int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
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{
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/* The non-secure entry point must be in DRAM */
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if (ns_entrypoint >= SUNXI_DRAM_BASE &&
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ns_entrypoint < SUNXI_DRAM_BASE + SUNXI_DRAM_SIZE)
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if (ns_entrypoint >= SUNXI_DRAM_BASE)
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return PSCI_E_SUCCESS;
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return PSCI_E_INVALID_ADDRESS;
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@ -12,6 +12,7 @@ void sunxi_cpu_off(unsigned int cluster, unsigned int core);
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void sunxi_cpu_on(unsigned int cluster, unsigned int core);
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void sunxi_disable_secondary_cpus(unsigned int primary_cpu);
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uint16_t sunxi_read_soc_id(void);
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void sunxi_security_setup(void);
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#endif /* __SUNXI_PRIVATE_H__ */
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@ -25,9 +25,9 @@
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*/
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void sunxi_security_setup(void)
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{
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#ifdef SUNXI_SPC_BASE
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int i;
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#ifdef SUNXI_SPC_BASE
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INFO("Configuring SPC Controller\n");
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/* SPC setup: set all devices to non-secure */
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for (i = 0; i < 6; i++)
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@ -27,7 +27,6 @@
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#define SUNXI_CPU_MBIST_BASE 0x01502000
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#define SUNXI_CPUCFG_BASE 0x01700000
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#define SUNXI_SYSCON_BASE 0x01c00000
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#define SUNXI_SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24)
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#define SUNXI_DMA_BASE 0x01c02000
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#define SUNXI_KEYMEM_BASE 0x01c0b000
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#define SUNXI_SMHC0_BASE 0x01c0f000
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