Merge "allwinner: Implement PSCI system suspend using SCPI" into integration
This commit is contained in:
commit
c335ad480d
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@ -21,6 +21,7 @@ PLAT_BL_COMMON_SOURCES := drivers/ti/uart/${ARCH}/16550_console.S \
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BL31_SOURCES += drivers/allwinner/axp/common.c \
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drivers/allwinner/sunxi_msgbox.c \
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drivers/arm/css/scpi/css_scpi.c \
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drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v2/gicv2_helpers.c \
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drivers/arm/gic/v2/gicv2_main.c \
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@ -40,6 +40,9 @@
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#define MAX_MMAP_REGIONS (3 + PLATFORM_MMAP_REGIONS)
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#define MAX_XLAT_TABLES 1
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#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \
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(SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200)
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#define PLAT_MAX_PWR_LVL_STATES U(2)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -10,6 +10,7 @@
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/arm/css/css_scpi.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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@ -17,6 +18,7 @@
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#include <plat/common/platform.h>
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#include <sunxi_cpucfg.h>
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#include <sunxi_def.h>
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#include <sunxi_mmap.h>
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#include <sunxi_private.h>
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@ -24,25 +26,88 @@
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#define SUNXI_WDOG0_CFG_REG (SUNXI_R_WDOG_BASE + 0x0014)
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#define SUNXI_WDOG0_MODE_REG (SUNXI_R_WDOG_BASE + 0x0018)
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#define mpidr_is_valid(mpidr) ( \
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MPIDR_AFFLVL3_VAL(mpidr) == 0 && \
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MPIDR_AFFLVL2_VAL(mpidr) == 0 && \
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MPIDR_AFFLVL1_VAL(mpidr) < PLATFORM_CLUSTER_COUNT && \
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MPIDR_AFFLVL0_VAL(mpidr) < PLATFORM_MAX_CPUS_PER_CLUSTER)
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#define CPU_PWR_LVL MPIDR_AFFLVL0
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#define CLUSTER_PWR_LVL MPIDR_AFFLVL1
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#define SYSTEM_PWR_LVL MPIDR_AFFLVL2
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#define CPU_PWR_STATE(state) \
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((state)->pwr_domain_state[CPU_PWR_LVL])
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#define CLUSTER_PWR_STATE(state) \
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((state)->pwr_domain_state[CLUSTER_PWR_LVL])
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#define SYSTEM_PWR_STATE(state) \
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((state)->pwr_domain_state[SYSTEM_PWR_LVL])
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#define mpidr_is_valid(mpidr) (plat_core_pos_by_mpidr(mpidr) >= 0)
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/*
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* The addresses for the SCP exception vectors are defined in the or1k
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* architecture specification.
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*/
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#define OR1K_VEC_FIRST 0x01
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#define OR1K_VEC_LAST 0x0e
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#define OR1K_VEC_ADDR(n) (0x100 * (n))
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/*
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* This magic value is the little-endian representation of the or1k
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* instruction "l.mfspr r2, r0, 0x12", which is guaranteed to be the
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* first instruction in the SCP firmware.
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*/
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#define SCP_FIRMWARE_MAGIC 0xb4400012
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static bool scpi_available;
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static inline scpi_power_state_t scpi_map_state(plat_local_state_t psci_state)
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{
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if (is_local_state_run(psci_state))
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return scpi_power_on;
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if (is_local_state_retn(psci_state))
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return scpi_power_retention;
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return scpi_power_off;
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}
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static void sunxi_cpu_standby(plat_local_state_t cpu_state)
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{
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u_register_t scr = read_scr_el3();
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assert(is_local_state_retn(cpu_state));
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write_scr_el3(scr | SCR_IRQ_BIT);
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wfi();
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write_scr_el3(scr);
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}
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static int sunxi_pwr_domain_on(u_register_t mpidr)
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{
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if (mpidr_is_valid(mpidr) == 0)
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return PSCI_E_INTERN_FAIL;
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sunxi_cpu_on(mpidr);
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if (scpi_available) {
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scpi_set_css_power_state(mpidr,
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scpi_power_on,
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scpi_power_on,
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scpi_power_on);
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} else {
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sunxi_cpu_on(mpidr);
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}
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return PSCI_E_SUCCESS;
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}
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static void sunxi_pwr_domain_off(const psci_power_state_t *target_state)
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{
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gicv2_cpuif_disable();
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plat_local_state_t cpu_pwr_state = CPU_PWR_STATE(target_state);
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plat_local_state_t cluster_pwr_state = CLUSTER_PWR_STATE(target_state);
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plat_local_state_t system_pwr_state = SYSTEM_PWR_STATE(target_state);
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if (is_local_state_off(cpu_pwr_state))
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gicv2_cpuif_disable();
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if (scpi_available) {
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scpi_set_css_power_state(read_mpidr(),
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scpi_map_state(cpu_pwr_state),
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scpi_map_state(cluster_pwr_state),
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scpi_map_state(system_pwr_state));
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}
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}
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static void __dead2 sunxi_pwr_down_wfi(const psci_power_state_t *target_state)
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@ -55,12 +120,26 @@ static void __dead2 sunxi_pwr_down_wfi(const psci_power_state_t *target_state)
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static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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if (is_local_state_off(SYSTEM_PWR_STATE(target_state)))
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gicv2_distif_init();
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if (is_local_state_off(CPU_PWR_STATE(target_state))) {
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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}
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static void __dead2 sunxi_system_off(void)
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{
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gicv2_cpuif_disable();
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if (scpi_available) {
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/* Send the power down request to the SCP */
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uint32_t ret = scpi_sys_power_state(scpi_system_shutdown);
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if (ret != SCP_OK)
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ERROR("PSCI: SCPI %s failed: %d\n", "shutdown", ret);
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}
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/* Turn off all secondary CPUs */
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sunxi_disable_secondary_cpus(read_mpidr());
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@ -74,6 +153,16 @@ static void __dead2 sunxi_system_off(void)
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static void __dead2 sunxi_system_reset(void)
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{
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gicv2_cpuif_disable();
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if (scpi_available) {
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/* Send the system reset request to the SCP */
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uint32_t ret = scpi_sys_power_state(scpi_system_reboot);
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if (ret != SCP_OK)
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ERROR("PSCI: SCPI %s failed: %d\n", "reboot", ret);
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}
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/* Reset the whole system when the watchdog times out */
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mmio_write_32(SUNXI_WDOG0_CFG_REG, 1);
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/* Enable the watchdog with the shortest timeout (0.5 seconds) */
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@ -86,6 +175,40 @@ static void __dead2 sunxi_system_reset(void)
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panic();
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}
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static int sunxi_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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unsigned int power_level = psci_get_pstate_pwrlvl(power_state);
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unsigned int type = psci_get_pstate_type(power_state);
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assert(req_state != NULL);
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if (power_level > PLAT_MAX_PWR_LVL)
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return PSCI_E_INVALID_PARAMS;
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if (type == PSTATE_TYPE_STANDBY) {
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/* Only one retention power state is supported. */
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if (psci_get_pstate_id(power_state) > 0)
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return PSCI_E_INVALID_PARAMS;
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/* The SoC cannot be suspended without losing state */
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if (power_level == SYSTEM_PWR_LVL)
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return PSCI_E_INVALID_PARAMS;
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for (unsigned int i = 0; i <= power_level; ++i)
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req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE;
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} else {
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/* Only one off power state is supported. */
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if (psci_get_pstate_id(power_state) > 0)
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return PSCI_E_INVALID_PARAMS;
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for (unsigned int i = 0; i <= power_level; ++i)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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}
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/* Higher power domain levels should all remain running */
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for (unsigned int i = power_level + 1; i <= PLAT_MAX_PWR_LVL; ++i)
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req_state->pwr_domain_state[i] = PSCI_LOCAL_STATE_RUN;
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return PSCI_E_SUCCESS;
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}
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static int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
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{
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/* The non-secure entry point must be in DRAM */
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@ -95,13 +218,45 @@ static int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
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return PSCI_E_INVALID_ADDRESS;
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}
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static void sunxi_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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assert(req_state);
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for (unsigned int i = 0; i <= PLAT_MAX_PWR_LVL; ++i)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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}
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static int sunxi_get_node_hw_state(u_register_t mpidr,
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unsigned int power_level)
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{
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unsigned int cluster_state, cpu_state;
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unsigned int cpu = MPIDR_AFFLVL0_VAL(mpidr);
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/* SoC power level (always on if PSCI works). */
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if (power_level == SYSTEM_PWR_LVL)
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return HW_ON;
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if (scpi_get_css_power_state(mpidr, &cpu_state, &cluster_state))
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return PSCI_E_NOT_SUPPORTED;
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/* Cluster power level (full power state available). */
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if (power_level == CLUSTER_PWR_LVL) {
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if (cluster_state == scpi_power_on)
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return HW_ON;
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if (cluster_state == scpi_power_retention)
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return HW_STANDBY;
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return HW_OFF;
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}
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/* CPU power level (one bit boolean for on or off). */
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return ((cpu_state & BIT(cpu)) != 0) ? HW_ON : HW_OFF;
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}
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static plat_psci_ops_t sunxi_psci_ops = {
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.cpu_standby = sunxi_cpu_standby,
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.pwr_domain_on = sunxi_pwr_domain_on,
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.pwr_domain_off = sunxi_pwr_domain_off,
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.pwr_domain_pwr_down_wfi = sunxi_pwr_down_wfi,
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.pwr_domain_on_finish = sunxi_pwr_domain_on_finish,
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.system_off = sunxi_system_off,
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.system_reset = sunxi_system_reset,
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.validate_power_state = sunxi_validate_power_state,
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.validate_ns_entrypoint = sunxi_validate_ns_entrypoint,
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};
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@ -110,13 +265,44 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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{
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assert(psci_ops);
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for (int cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu += 1) {
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/* Program all CPU entry points. */
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for (unsigned int cpu = 0; cpu < PLATFORM_CORE_COUNT; ++cpu) {
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mmio_write_32(SUNXI_CPUCFG_RVBAR_LO_REG(cpu),
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sec_entrypoint & 0xffffffff);
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mmio_write_32(SUNXI_CPUCFG_RVBAR_HI_REG(cpu),
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sec_entrypoint >> 32);
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}
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/* Check for a valid SCP firmware, and boot the SCP if found. */
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if (mmio_read_32(SUNXI_SCP_BASE) == SCP_FIRMWARE_MAGIC) {
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/* Program SCP exception vectors to the firmware entrypoint. */
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for (unsigned int i = OR1K_VEC_FIRST; i <= OR1K_VEC_LAST; ++i) {
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uint32_t vector = SUNXI_SRAM_A2_BASE + OR1K_VEC_ADDR(i);
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uint32_t offset = SUNXI_SCP_BASE - vector;
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mmio_write_32(vector, offset >> 2);
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clean_dcache_range(vector, sizeof(uint32_t));
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}
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/* Take the SCP out of reset. */
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mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));
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/* Wait for the SCP firmware to boot. */
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if (scpi_wait_ready() == 0)
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scpi_available = true;
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}
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NOTICE("PSCI: System suspend is %s\n",
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scpi_available ? "available via SCPI" : "unavailable");
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if (scpi_available) {
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/* Suspend is only available via SCPI. */
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sunxi_psci_ops.pwr_domain_suspend = sunxi_pwr_domain_off;
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sunxi_psci_ops.pwr_domain_suspend_finish = sunxi_pwr_domain_on_finish;
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sunxi_psci_ops.get_sys_suspend_power_state = sunxi_get_sys_suspend_power_state;
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sunxi_psci_ops.get_node_hw_state = sunxi_get_node_hw_state;
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} else {
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/* This is only needed when SCPI is unavailable. */
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sunxi_psci_ops.pwr_domain_pwr_down_wfi = sunxi_pwr_down_wfi;
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}
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*psci_ops = &sunxi_psci_ops;
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return 0;
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