Merge changes from topic "sunxi-split-psci" into integration
* changes: allwinner: Split native and SCPI-based PSCI implementations allwinner: psci: Improve system shutdown/reset sequence allwinner: psci: Drop .pwr_domain_pwr_down_wfi callback allwinner: Separate code to power off self and other CPUs
This commit is contained in:
André Przywara
TrustedFirmware Code Review
commit
c36e2d488e
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@ -30,7 +30,9 @@ BL31_SOURCES += drivers/allwinner/axp/common.c \
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plat/common/plat_psci_common.c \
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${AW_PLAT}/common/sunxi_bl31_setup.c \
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${AW_PLAT}/common/sunxi_cpu_ops.c \
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${AW_PLAT}/common/sunxi_native_pm.c \
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${AW_PLAT}/common/sunxi_pm.c \
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${AW_PLAT}/common/sunxi_scpi_pm.c \
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${AW_PLAT}/${PLAT}/sunxi_power.c \
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${AW_PLAT}/common/sunxi_security.c \
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${AW_PLAT}/common/sunxi_topology.c
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -7,13 +7,19 @@
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#ifndef SUNXI_PRIVATE_H
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#define SUNXI_PRIVATE_H
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#include <lib/psci/psci.h>
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void sunxi_configure_mmu_el3(int flags);
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void sunxi_cpu_on(u_register_t mpidr);
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void sunxi_cpu_off(u_register_t mpidr);
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void sunxi_disable_secondary_cpus(u_register_t primary_mpidr);
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void sunxi_cpu_power_off_others(void);
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void sunxi_cpu_power_off_self(void);
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void sunxi_power_down(void);
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void sunxi_set_native_psci_ops(const plat_psci_ops_t **psci_ops);
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int sunxi_set_scpi_psci_ops(const plat_psci_ops_t **psci_ops);
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int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint);
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int sunxi_pmic_setup(uint16_t socid, const void *fdt);
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void sunxi_security_setup(void);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -45,7 +45,8 @@ static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core)
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x00);
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}
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void sunxi_cpu_off(u_register_t mpidr)
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/* We can't turn ourself off like this, but it works for other cores. */
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static void sunxi_cpu_off(u_register_t mpidr)
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{
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unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr);
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unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
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@ -54,23 +55,22 @@ void sunxi_cpu_off(u_register_t mpidr)
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/* Deassert DBGPWRDUP */
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mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
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/* Activate the core output clamps, but not for core 0. */
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if (core != 0)
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mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
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/* Assert CPU power-on reset */
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mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
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/* Remove power from the CPU */
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sunxi_cpu_disable_power(cluster, core);
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}
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/* We can't turn ourself off like this, but it works for other cores. */
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if (read_mpidr() != mpidr) {
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/* Activate the core output clamps, but not for core 0. */
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if (core != 0)
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mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster),
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BIT(core));
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/* Assert CPU power-on reset */
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mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
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/* Remove power from the CPU */
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sunxi_cpu_disable_power(cluster, core);
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return;
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}
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void sunxi_cpu_power_off_self(void)
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{
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u_register_t mpidr = read_mpidr();
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unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
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/* Simplifies assembly, all SoCs so far are single cluster anyway. */
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assert(cluster == 0);
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assert(MPIDR_AFFLVL1_VAL(mpidr) == 0);
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/*
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* If we are supposed to turn ourself off, tell the arisc SCP
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@ -106,8 +106,9 @@ void sunxi_cpu_on(u_register_t mpidr)
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mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
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}
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void sunxi_disable_secondary_cpus(u_register_t primary_mpidr)
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void sunxi_cpu_power_off_others(void)
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{
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u_register_t self = read_mpidr();
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unsigned int cluster;
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unsigned int core;
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@ -116,7 +117,7 @@ void sunxi_disable_secondary_cpus(u_register_t primary_mpidr)
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u_register_t mpidr = (cluster << MPIDR_AFF1_SHIFT) |
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(core << MPIDR_AFF0_SHIFT) |
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BIT(31);
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if (mpidr != primary_mpidr)
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if (mpidr != self)
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sunxi_cpu_off(mpidr);
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}
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}
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@ -0,0 +1,81 @@
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/*
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* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <sunxi_mmap.h>
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#include <sunxi_private.h>
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#define SUNXI_WDOG0_CTRL_REG (SUNXI_R_WDOG_BASE + 0x0010)
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#define SUNXI_WDOG0_CFG_REG (SUNXI_R_WDOG_BASE + 0x0014)
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#define SUNXI_WDOG0_MODE_REG (SUNXI_R_WDOG_BASE + 0x0018)
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static int sunxi_pwr_domain_on(u_register_t mpidr)
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{
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sunxi_cpu_on(mpidr);
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return PSCI_E_SUCCESS;
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}
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static void sunxi_pwr_domain_off(const psci_power_state_t *target_state)
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{
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gicv2_cpuif_disable();
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sunxi_cpu_power_off_self();
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}
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static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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static void __dead2 sunxi_system_off(void)
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{
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gicv2_cpuif_disable();
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/* Attempt to power down the board (may not return) */
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sunxi_power_down();
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/* Turn off all CPUs */
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sunxi_cpu_power_off_others();
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sunxi_cpu_power_off_self();
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psci_power_down_wfi();
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}
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static void __dead2 sunxi_system_reset(void)
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{
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gicv2_cpuif_disable();
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/* Reset the whole system when the watchdog times out */
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mmio_write_32(SUNXI_WDOG0_CFG_REG, 1);
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/* Enable the watchdog with the shortest timeout (0.5 seconds) */
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mmio_write_32(SUNXI_WDOG0_MODE_REG, (0 << 4) | 1);
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/* Wait for twice the watchdog timeout before panicking */
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mdelay(1000);
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ERROR("PSCI: System reset failed\n");
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panic();
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}
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static const plat_psci_ops_t sunxi_native_psci_ops = {
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.pwr_domain_on = sunxi_pwr_domain_on,
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.pwr_domain_off = sunxi_pwr_domain_off,
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.pwr_domain_on_finish = sunxi_pwr_domain_on_finish,
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.system_off = sunxi_system_off,
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.system_reset = sunxi_system_reset,
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.validate_ns_entrypoint = sunxi_validate_ns_entrypoint,
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};
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void sunxi_set_native_psci_ops(const plat_psci_ops_t **psci_ops)
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{
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*psci_ops = &sunxi_native_psci_ops;
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}
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@ -8,203 +8,14 @@
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/arm/css/css_scpi.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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#include <sunxi_cpucfg.h>
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#include <sunxi_def.h>
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#include <sunxi_mmap.h>
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#include <sunxi_private.h>
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#define SUNXI_WDOG0_CTRL_REG (SUNXI_R_WDOG_BASE + 0x0010)
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#define SUNXI_WDOG0_CFG_REG (SUNXI_R_WDOG_BASE + 0x0014)
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#define SUNXI_WDOG0_MODE_REG (SUNXI_R_WDOG_BASE + 0x0018)
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#define CPU_PWR_LVL MPIDR_AFFLVL0
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#define CLUSTER_PWR_LVL MPIDR_AFFLVL1
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#define SYSTEM_PWR_LVL MPIDR_AFFLVL2
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#define CPU_PWR_STATE(state) \
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((state)->pwr_domain_state[CPU_PWR_LVL])
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#define CLUSTER_PWR_STATE(state) \
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((state)->pwr_domain_state[CLUSTER_PWR_LVL])
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#define SYSTEM_PWR_STATE(state) \
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((state)->pwr_domain_state[SYSTEM_PWR_LVL])
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/*
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* The addresses for the SCP exception vectors are defined in the or1k
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* architecture specification.
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*/
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#define OR1K_VEC_FIRST 0x01
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#define OR1K_VEC_LAST 0x0e
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#define OR1K_VEC_ADDR(n) (0x100 * (n))
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/*
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* This magic value is the little-endian representation of the or1k
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* instruction "l.mfspr r2, r0, 0x12", which is guaranteed to be the
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* first instruction in the SCP firmware.
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*/
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#define SCP_FIRMWARE_MAGIC 0xb4400012
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static bool scpi_available;
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static inline scpi_power_state_t scpi_map_state(plat_local_state_t psci_state)
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{
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if (is_local_state_run(psci_state))
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return scpi_power_on;
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if (is_local_state_retn(psci_state))
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return scpi_power_retention;
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return scpi_power_off;
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}
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static void sunxi_cpu_standby(plat_local_state_t cpu_state)
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{
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u_register_t scr = read_scr_el3();
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assert(is_local_state_retn(cpu_state));
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write_scr_el3(scr | SCR_IRQ_BIT);
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wfi();
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write_scr_el3(scr);
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}
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static int sunxi_pwr_domain_on(u_register_t mpidr)
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{
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if (scpi_available) {
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scpi_set_css_power_state(mpidr,
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scpi_power_on,
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scpi_power_on,
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scpi_power_on);
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} else {
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sunxi_cpu_on(mpidr);
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}
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return PSCI_E_SUCCESS;
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}
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static void sunxi_pwr_domain_off(const psci_power_state_t *target_state)
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{
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plat_local_state_t cpu_pwr_state = CPU_PWR_STATE(target_state);
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plat_local_state_t cluster_pwr_state = CLUSTER_PWR_STATE(target_state);
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plat_local_state_t system_pwr_state = SYSTEM_PWR_STATE(target_state);
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if (is_local_state_off(cpu_pwr_state))
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gicv2_cpuif_disable();
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if (scpi_available) {
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scpi_set_css_power_state(read_mpidr(),
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scpi_map_state(cpu_pwr_state),
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scpi_map_state(cluster_pwr_state),
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scpi_map_state(system_pwr_state));
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}
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}
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static void __dead2 sunxi_pwr_down_wfi(const psci_power_state_t *target_state)
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{
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sunxi_cpu_off(read_mpidr());
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while (1)
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wfi();
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}
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static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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if (is_local_state_off(SYSTEM_PWR_STATE(target_state)))
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gicv2_distif_init();
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if (is_local_state_off(CPU_PWR_STATE(target_state))) {
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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}
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static void __dead2 sunxi_system_off(void)
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{
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gicv2_cpuif_disable();
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if (scpi_available) {
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/* Send the power down request to the SCP */
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uint32_t ret = scpi_sys_power_state(scpi_system_shutdown);
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if (ret != SCP_OK)
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ERROR("PSCI: SCPI %s failed: %d\n", "shutdown", ret);
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}
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/* Turn off all secondary CPUs */
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sunxi_disable_secondary_cpus(read_mpidr());
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sunxi_power_down();
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udelay(1000);
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ERROR("PSCI: Cannot turn off system, halting\n");
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wfi();
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panic();
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}
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static void __dead2 sunxi_system_reset(void)
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{
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gicv2_cpuif_disable();
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if (scpi_available) {
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/* Send the system reset request to the SCP */
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uint32_t ret = scpi_sys_power_state(scpi_system_reboot);
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if (ret != SCP_OK)
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ERROR("PSCI: SCPI %s failed: %d\n", "reboot", ret);
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}
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/* Reset the whole system when the watchdog times out */
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mmio_write_32(SUNXI_WDOG0_CFG_REG, 1);
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/* Enable the watchdog with the shortest timeout (0.5 seconds) */
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mmio_write_32(SUNXI_WDOG0_MODE_REG, (0 << 4) | 1);
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/* Wait for twice the watchdog timeout before panicking */
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mdelay(1000);
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ERROR("PSCI: System reset failed\n");
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wfi();
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panic();
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}
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static int sunxi_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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unsigned int power_level = psci_get_pstate_pwrlvl(power_state);
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unsigned int type = psci_get_pstate_type(power_state);
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assert(req_state != NULL);
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if (power_level > PLAT_MAX_PWR_LVL)
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return PSCI_E_INVALID_PARAMS;
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if (type == PSTATE_TYPE_STANDBY) {
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/* Only one retention power state is supported. */
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if (psci_get_pstate_id(power_state) > 0)
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return PSCI_E_INVALID_PARAMS;
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/* The SoC cannot be suspended without losing state */
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if (power_level == SYSTEM_PWR_LVL)
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return PSCI_E_INVALID_PARAMS;
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for (unsigned int i = 0; i <= power_level; ++i)
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req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE;
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} else {
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/* Only one off power state is supported. */
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if (psci_get_pstate_id(power_state) > 0)
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return PSCI_E_INVALID_PARAMS;
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for (unsigned int i = 0; i <= power_level; ++i)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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}
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/* Higher power domain levels should all remain running */
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for (unsigned int i = power_level + 1; i <= PLAT_MAX_PWR_LVL; ++i)
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req_state->pwr_domain_state[i] = PSCI_LOCAL_STATE_RUN;
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return PSCI_E_SUCCESS;
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}
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static int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
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int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
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{
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/* The non-secure entry point must be in DRAM */
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if (ns_entrypoint < SUNXI_DRAM_BASE) {
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@ -214,25 +25,6 @@ static int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
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return PSCI_E_SUCCESS;
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}
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static void sunxi_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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assert(req_state);
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for (unsigned int i = 0; i <= PLAT_MAX_PWR_LVL; ++i)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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}
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static plat_psci_ops_t sunxi_psci_ops = {
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.cpu_standby = sunxi_cpu_standby,
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.pwr_domain_on = sunxi_pwr_domain_on,
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.pwr_domain_off = sunxi_pwr_domain_off,
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.pwr_domain_on_finish = sunxi_pwr_domain_on_finish,
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.system_off = sunxi_system_off,
|
||||
.system_reset = sunxi_system_reset,
|
||||
.validate_power_state = sunxi_validate_power_state,
|
||||
.validate_ns_entrypoint = sunxi_validate_ns_entrypoint,
|
||||
};
|
||||
|
||||
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
||||
const plat_psci_ops_t **psci_ops)
|
||||
{
|
||||
|
|
@ -246,36 +38,12 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
|||
sec_entrypoint >> 32);
|
||||
}
|
||||
|
||||
/* Check for a valid SCP firmware, and boot the SCP if found. */
|
||||
if (mmio_read_32(SUNXI_SCP_BASE) == SCP_FIRMWARE_MAGIC) {
|
||||
/* Program SCP exception vectors to the firmware entrypoint. */
|
||||
for (unsigned int i = OR1K_VEC_FIRST; i <= OR1K_VEC_LAST; ++i) {
|
||||
uint32_t vector = SUNXI_SRAM_A2_BASE + OR1K_VEC_ADDR(i);
|
||||
uint32_t offset = SUNXI_SCP_BASE - vector;
|
||||
|
||||
mmio_write_32(vector, offset >> 2);
|
||||
clean_dcache_range(vector, sizeof(uint32_t));
|
||||
}
|
||||
/* Take the SCP out of reset. */
|
||||
mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));
|
||||
/* Wait for the SCP firmware to boot. */
|
||||
if (scpi_wait_ready() == 0)
|
||||
scpi_available = true;
|
||||
}
|
||||
|
||||
NOTICE("PSCI: System suspend is %s\n",
|
||||
scpi_available ? "available via SCPI" : "unavailable");
|
||||
if (scpi_available) {
|
||||
/* Suspend is only available via SCPI. */
|
||||
sunxi_psci_ops.pwr_domain_suspend = sunxi_pwr_domain_off;
|
||||
sunxi_psci_ops.pwr_domain_suspend_finish = sunxi_pwr_domain_on_finish;
|
||||
sunxi_psci_ops.get_sys_suspend_power_state = sunxi_get_sys_suspend_power_state;
|
||||
if (sunxi_set_scpi_psci_ops(psci_ops) == 0) {
|
||||
INFO("PSCI: Suspend is available via SCPI\n");
|
||||
} else {
|
||||
/* This is only needed when SCPI is unavailable. */
|
||||
sunxi_psci_ops.pwr_domain_pwr_down_wfi = sunxi_pwr_down_wfi;
|
||||
INFO("PSCI: Suspend is unavailable\n");
|
||||
sunxi_set_native_psci_ops(psci_ops);
|
||||
}
|
||||
|
||||
*psci_ops = &sunxi_psci_ops;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,223 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/arm/css/css_scpi.h>
|
||||
#include <drivers/arm/gicv2.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/psci/psci.h>
|
||||
|
||||
#include <sunxi_mmap.h>
|
||||
#include <sunxi_private.h>
|
||||
|
||||
/*
|
||||
* The addresses for the SCP exception vectors are defined in the or1k
|
||||
* architecture specification.
|
||||
*/
|
||||
#define OR1K_VEC_FIRST 0x01
|
||||
#define OR1K_VEC_LAST 0x0e
|
||||
#define OR1K_VEC_ADDR(n) (0x100 * (n))
|
||||
|
||||
/*
|
||||
* This magic value is the little-endian representation of the or1k
|
||||
* instruction "l.mfspr r2, r0, 0x12", which is guaranteed to be the
|
||||
* first instruction in the SCP firmware.
|
||||
*/
|
||||
#define SCP_FIRMWARE_MAGIC 0xb4400012
|
||||
|
||||
#define CPU_PWR_LVL MPIDR_AFFLVL0
|
||||
#define CLUSTER_PWR_LVL MPIDR_AFFLVL1
|
||||
#define SYSTEM_PWR_LVL MPIDR_AFFLVL2
|
||||
|
||||
#define CPU_PWR_STATE(state) \
|
||||
((state)->pwr_domain_state[CPU_PWR_LVL])
|
||||
#define CLUSTER_PWR_STATE(state) \
|
||||
((state)->pwr_domain_state[CLUSTER_PWR_LVL])
|
||||
#define SYSTEM_PWR_STATE(state) \
|
||||
((state)->pwr_domain_state[SYSTEM_PWR_LVL])
|
||||
|
||||
static inline scpi_power_state_t scpi_map_state(plat_local_state_t psci_state)
|
||||
{
|
||||
if (is_local_state_run(psci_state)) {
|
||||
return scpi_power_on;
|
||||
}
|
||||
if (is_local_state_retn(psci_state)) {
|
||||
return scpi_power_retention;
|
||||
}
|
||||
return scpi_power_off;
|
||||
}
|
||||
|
||||
static void sunxi_cpu_standby(plat_local_state_t cpu_state)
|
||||
{
|
||||
u_register_t scr = read_scr_el3();
|
||||
|
||||
assert(is_local_state_retn(cpu_state));
|
||||
|
||||
write_scr_el3(scr | SCR_IRQ_BIT);
|
||||
wfi();
|
||||
write_scr_el3(scr);
|
||||
}
|
||||
|
||||
static int sunxi_pwr_domain_on(u_register_t mpidr)
|
||||
{
|
||||
scpi_set_css_power_state(mpidr,
|
||||
scpi_power_on,
|
||||
scpi_power_on,
|
||||
scpi_power_on);
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
static void sunxi_pwr_domain_off(const psci_power_state_t *target_state)
|
||||
{
|
||||
plat_local_state_t cpu_pwr_state = CPU_PWR_STATE(target_state);
|
||||
plat_local_state_t cluster_pwr_state = CLUSTER_PWR_STATE(target_state);
|
||||
plat_local_state_t system_pwr_state = SYSTEM_PWR_STATE(target_state);
|
||||
|
||||
if (is_local_state_off(cpu_pwr_state)) {
|
||||
gicv2_cpuif_disable();
|
||||
}
|
||||
|
||||
scpi_set_css_power_state(read_mpidr(),
|
||||
scpi_map_state(cpu_pwr_state),
|
||||
scpi_map_state(cluster_pwr_state),
|
||||
scpi_map_state(system_pwr_state));
|
||||
}
|
||||
|
||||
static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
||||
{
|
||||
if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) {
|
||||
gicv2_distif_init();
|
||||
}
|
||||
if (is_local_state_off(CPU_PWR_STATE(target_state))) {
|
||||
gicv2_pcpu_distif_init();
|
||||
gicv2_cpuif_enable();
|
||||
}
|
||||
}
|
||||
|
||||
static void __dead2 sunxi_system_off(void)
|
||||
{
|
||||
uint32_t ret;
|
||||
|
||||
gicv2_cpuif_disable();
|
||||
|
||||
/* Send the power down request to the SCP. */
|
||||
ret = scpi_sys_power_state(scpi_system_shutdown);
|
||||
if (ret != SCP_OK) {
|
||||
ERROR("PSCI: SCPI %s failed: %d\n", "shutdown", ret);
|
||||
}
|
||||
|
||||
psci_power_down_wfi();
|
||||
}
|
||||
|
||||
static void __dead2 sunxi_system_reset(void)
|
||||
{
|
||||
uint32_t ret;
|
||||
|
||||
gicv2_cpuif_disable();
|
||||
|
||||
/* Send the system reset request to the SCP. */
|
||||
ret = scpi_sys_power_state(scpi_system_reboot);
|
||||
if (ret != SCP_OK) {
|
||||
ERROR("PSCI: SCPI %s failed: %d\n", "reboot", ret);
|
||||
}
|
||||
|
||||
psci_power_down_wfi();
|
||||
}
|
||||
|
||||
static int sunxi_validate_power_state(unsigned int power_state,
|
||||
psci_power_state_t *req_state)
|
||||
{
|
||||
unsigned int power_level = psci_get_pstate_pwrlvl(power_state);
|
||||
unsigned int type = psci_get_pstate_type(power_state);
|
||||
|
||||
assert(req_state != NULL);
|
||||
|
||||
if (power_level > PLAT_MAX_PWR_LVL) {
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
}
|
||||
|
||||
if (type == PSTATE_TYPE_STANDBY) {
|
||||
/* Only one retention power state is supported. */
|
||||
if (psci_get_pstate_id(power_state) > 0) {
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
}
|
||||
/* The SoC cannot be suspended without losing state */
|
||||
if (power_level == SYSTEM_PWR_LVL) {
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
}
|
||||
for (unsigned int i = 0; i <= power_level; ++i) {
|
||||
req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE;
|
||||
}
|
||||
} else {
|
||||
/* Only one off power state is supported. */
|
||||
if (psci_get_pstate_id(power_state) > 0) {
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
}
|
||||
for (unsigned int i = 0; i <= power_level; ++i) {
|
||||
req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
|
||||
}
|
||||
}
|
||||
/* Higher power domain levels should all remain running */
|
||||
for (unsigned int i = power_level + 1; i <= PLAT_MAX_PWR_LVL; ++i) {
|
||||
req_state->pwr_domain_state[i] = PSCI_LOCAL_STATE_RUN;
|
||||
}
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
static void sunxi_get_sys_suspend_power_state(psci_power_state_t *req_state)
|
||||
{
|
||||
assert(req_state != NULL);
|
||||
|
||||
for (unsigned int i = 0; i <= PLAT_MAX_PWR_LVL; ++i) {
|
||||
req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
|
||||
}
|
||||
}
|
||||
|
||||
static const plat_psci_ops_t sunxi_scpi_psci_ops = {
|
||||
.cpu_standby = sunxi_cpu_standby,
|
||||
.pwr_domain_on = sunxi_pwr_domain_on,
|
||||
.pwr_domain_off = sunxi_pwr_domain_off,
|
||||
.pwr_domain_suspend = sunxi_pwr_domain_off,
|
||||
.pwr_domain_on_finish = sunxi_pwr_domain_on_finish,
|
||||
.pwr_domain_suspend_finish = sunxi_pwr_domain_on_finish,
|
||||
.system_off = sunxi_system_off,
|
||||
.system_reset = sunxi_system_reset,
|
||||
.validate_power_state = sunxi_validate_power_state,
|
||||
.validate_ns_entrypoint = sunxi_validate_ns_entrypoint,
|
||||
.get_sys_suspend_power_state = sunxi_get_sys_suspend_power_state,
|
||||
};
|
||||
|
||||
int sunxi_set_scpi_psci_ops(const plat_psci_ops_t **psci_ops)
|
||||
{
|
||||
*psci_ops = &sunxi_scpi_psci_ops;
|
||||
|
||||
/* Check for a valid SCP firmware. */
|
||||
if (mmio_read_32(SUNXI_SCP_BASE) != SCP_FIRMWARE_MAGIC) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Program SCP exception vectors to the firmware entrypoint. */
|
||||
for (unsigned int i = OR1K_VEC_FIRST; i <= OR1K_VEC_LAST; ++i) {
|
||||
uint32_t vector = SUNXI_SRAM_A2_BASE + OR1K_VEC_ADDR(i);
|
||||
uint32_t offset = SUNXI_SCP_BASE - vector;
|
||||
|
||||
mmio_write_32(vector, offset >> 2);
|
||||
clean_dcache_range(vector, sizeof(uint32_t));
|
||||
}
|
||||
|
||||
/* Take the SCP out of reset. */
|
||||
mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));
|
||||
|
||||
/* Wait for the SCP firmware to boot. */
|
||||
return scpi_wait_ready();
|
||||
}
|
||||
Loading…
Reference in New Issue