Merge pull request #1308 from soby-mathew/sm/doc_dyn_cfg
Docs: Update design guide for dynamic config
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c3e34a9e01
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@ -77,11 +77,57 @@ one or more of these memory regions.
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The sections below provide the following details:
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- dynamic configuration of Boot Loader stages
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- initialization and execution of the first three stages during cold boot
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- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for
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AArch32) entrypoint requirements for use by alternative Trusted Boot
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Firmware in place of the provided BL1 and BL2
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Dynamic Configuration during cold boot
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Each of the Boot Loader stages may be dynamically configured if required by the
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platform. The Boot Loader stage may optionally specify a firmware
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configuration file and/or hardware configuration file as listed below:
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- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader
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stages and also by the Normal World Rich OS.
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- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1
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and BL2.
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- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31.
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- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS
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(BL32).
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- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted
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firmware (BL33).
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The Arm development platforms use the Flattened Device Tree format for the
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dynamic configuration files.
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Each Boot Loader stage can pass up to 4 arguments via registers to the next
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stage. BL2 passes the list of the next images to execute to the *EL3 Runtime
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Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other
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arguments are platform defined. The Arm development platforms use the following
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convention:
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- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This
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structure contains the memory layout available to BL2.
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- When dynamic configuration files are present, the firmware configuration for
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the next Boot Loader stage is populated in the first available argument and
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the generic hardware configuration is passed the next available argument.
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For example,
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- If TB_FW_CONFIG is loaded by BL1, then its address is passed in ``arg0``
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to BL2.
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- If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to
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BL2. Note, ``arg1`` is already used for meminfo_t.
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- If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1``
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to BL31. Note, ``arg0`` is used to pass the list of executable images.
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- Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is
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passed in ``arg2`` to BL31.
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- For other BL3x images, if the firmware configuration file is loaded by
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BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded
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then its address is passed in ``arg1``.
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BL1
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~~~
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@ -261,6 +307,9 @@ On ARM platforms, BL1 performs the following platform initializations:
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- Enable the MMU and map the memory it needs to access.
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- Configure any required platform storage to load the next bootloader image
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(BL2).
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- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then
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load it to the platform defined address and make it available to BL2 via
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``arg0``.
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Firmware Update detection and execution
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -287,10 +336,10 @@ In the normal boot flow, BL1 execution continues as follows:
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"Booting Trusted Firmware"
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#. BL1 determines the amount of free trusted SRAM memory available by
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calculating the extent of its own data section, which also resides in
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trusted SRAM. BL1 loads a BL2 raw binary image from platform storage, at a
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platform-specific base address. If the BL2 image file is not present or if
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#. BL1 loads a BL2 raw binary image from platform storage, at a
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platform-specific base address. Prior to the load, BL1 invokes
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``bl1_plat_handle_pre_image_load()`` which allows the platform to update or
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use the image information. If the BL2 image file is not present or if
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there is not enough free trusted SRAM the following error message is
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printed:
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@ -298,18 +347,15 @@ In the normal boot flow, BL1 execution continues as follows:
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"Failed to load BL2 firmware."
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BL1 calculates the amount of Trusted SRAM that can be used by the BL2
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image. The exact load location of the image is provided as a base address
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in the platform header. Further description of the memory layout can be
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found later in this document.
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#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended
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for platforms to take further action after image load. This function must
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populate the necessary arguments for BL2, which may also include the memory
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layout. Further description of the memory layout can be found later
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in this document.
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#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at
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Secure SVC mode (for AArch32), starting from its load address.
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#. BL1 also passes information about the amount of trusted SRAM used and
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available for use. This information is populated at a platform-specific
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memory address.
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BL2
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~~~
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@ -344,6 +390,8 @@ On ARM platforms, BL2 performs the following platform initializations:
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EL3 Runtime Software and populate it.
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- Define the extents of memory available for loading each subsequent
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bootloader image.
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- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``,
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then parse it.
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Image loading in BL2
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^^^^^^^^^^^^^^^^^^^^
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@ -356,6 +404,12 @@ by the platform. BL2 passes the list of executable images provided by the
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platform to the next handover BL image. By default, this flag is disabled for
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AArch64 and the AArch32 build is supported only if this flag is enabled.
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The list of loadable images provided by the platform may also contain
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dynamic configuration files. The files are loaded and can be parsed as
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needed in the ``bl2_plat_handle_post_image_load()`` function. These
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configuration files can be passed to next Boot Loader stages as arguments
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by updating the corresponding entrypoint information in this function.
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SCP\_BL2 (System Control Processor Firmware) image load
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -1791,32 +1845,44 @@ layout of the other images in Trusted SRAM.
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| BL1 (ro) |
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0x00000000 +----------+
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**FVP with TSP in Trusted DRAM:**
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**FVP with TSP in Trusted DRAM with TB_FW_CONFIG and HW_CONFIG :**
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::
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Trusted DRAM
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0x08000000 +----------+
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| BL32 |
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0x06000000 +----------+
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DRAM
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0xffffffff +--------------+
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: :
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|--------------|
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| HW_CONFIG |
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0x83000000 |--------------| (non-secure)
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0x80000000 +--------------+
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Trusted SRAM
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0x04040000 +----------+ loaded by BL2 ------------------
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| BL1 (rw) | <<<<<<<<<<<<< | BL31 NOBITS |
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|----------| <<<<<<<<<<<<< |----------------|
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| | <<<<<<<<<<<<< | BL31 PROGBITS |
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|----------| ------------------
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| BL2 |
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|----------|
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0x04001000 +----------+
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| Shared |
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0x04000000 +----------+
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Trusted DRAM
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0x08000000 +--------------+
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| BL32 |
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0x06000000 +--------------+
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Trusted ROM
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0x04000000 +----------+
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| BL1 (ro) |
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0x00000000 +----------+
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Trusted SRAM
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0x04040000 +--------------+ loaded by BL2 ------------------
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| BL1 (rw) | <<<<<<<<<<<<< | BL31 NOBITS |
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|--------------| <<<<<<<<<<<<< |----------------|
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| | <<<<<<<<<<<<< | BL31 PROGBITS |
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|--------------| ------------------
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| BL2 |
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|--------------|
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| |
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|--------------|
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| TB_FW_CONFIG |
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|--------------|
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0x04001000 +--------------+
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| Shared |
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0x04000000 +--------------+
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Trusted ROM
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0x04000000 +--------------+
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| BL1 (ro) |
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0x00000000 +--------------+
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**FVP with TSP in TZC-Secured DRAM:**
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@ -1824,7 +1890,7 @@ layout of the other images in Trusted SRAM.
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DRAM
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0xffffffff +----------+
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| BL32 | (secure)
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| BL32 | (secure)
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0xff000000 +----------+
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: : (non-secure)
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@ -1881,7 +1947,7 @@ layout of the other images in Trusted SRAM.
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DRAM
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0xFFE00000 +----------+
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| BL32 | (secure)
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| BL32 | (secure)
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0xFF000000 |----------|
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: : (non-secure)
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@ -2663,7 +2729,7 @@ References
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--------------
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*Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.*
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*Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.*
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.. _Reset Design: ./reset-design.rst
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.. _Porting Guide: ./porting-guide.rst
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@ -1076,20 +1076,16 @@ warm boot. For each CPU, BL1 is responsible for the following tasks:
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allocation to BL2
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meminfo.free_size = Size of secure RAM available for allocation to BL2
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BL1 places this ``meminfo`` structure at the beginning of the free memory
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available for its use. Since BL1 cannot allocate memory dynamically at the
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moment, its free memory will be available for BL2's use as-is. However, this
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means that BL2 must read the ``meminfo`` structure before it starts using its
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free memory (this is discussed in Section 3.2).
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By default, BL1 places this ``meminfo`` structure at the beginning of the
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free memory available for its use. Since BL1 cannot allocate memory
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dynamically at the moment, its free memory will be available for BL2's use
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as-is. However, this means that BL2 must read the ``meminfo`` structure
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before it starts using its free memory (this is discussed in Section 3.2).
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In future releases of the ARM Trusted Firmware it will be possible for
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the platform to decide where it wants to place the ``meminfo`` structure for
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BL2.
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BL1 implements the ``bl1_init_bl2_mem_layout()`` function to populate the
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BL2 ``meminfo`` structure. The platform may override this implementation, for
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example if the platform wants to restrict the amount of memory visible to
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BL2. Details of how to do this are given below.
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It is possible for the platform to decide where it wants to place the
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``meminfo`` structure for BL2 or restrict the amount of memory visible to
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BL2 by overriding the weak default implementation of
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``bl1_plat_handle_post_image_load`` API.
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The following functions need to be implemented by the platform port to enable
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BL1 to perform the above tasks.
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@ -1264,6 +1260,12 @@ This function can be used by the platforms to update/use image information
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corresponding to ``image_id``. This function is invoked in BL1, both in cold
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boot and FWU code path, after loading and authenticating the image.
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The default weak implementation of this function calculates the amount of
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Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t``
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structure at the beginning of this free memory and populates it. The address
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of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint
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information to BL2.
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Function : bl1\_plat\_fwu\_done() [optional]
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@ -776,6 +776,19 @@ ARM FVP platform specific build options
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for functions that wait for an arbitrary time length (udelay and mdelay).
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The default value is 0.
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- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
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to DTB and packaged in FIP as the HW_CONFIG. See `Firmware Design`_ for
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details on HW_CONFIG. By default, this is initialized to a sensible DTS
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file in ``fdts/`` folder depending on other build options. But some cases,
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like shifted affinity format for MPIDR, cannot be detected at build time
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and this option is needed to specify the appropriate DTS file.
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- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
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FIP. See `Firmware Design`_ for details on HW_CONFIG. This option is
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similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
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HW_CONFIG blob instead of the DTS file. This option is useful to override
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the default HW_CONFIG selected by the build system.
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Debugging options
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~~~~~~~~~~~~~~~~~
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