Merge changes from topic "tc0_sel2_spmc" into integration
* changes: lib: el3_runtime: Fix SPE system registers in el2_sysregs_context lib: el3_runtime: Conditionally save/restore EL2 NEVE registers lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_context
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commit
c4d919eeb9
2
Makefile
2
Makefile
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@ -865,6 +865,7 @@ $(eval $(call assert_booleans,\
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CTX_INCLUDE_PAUTH_REGS \
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CTX_INCLUDE_MTE_REGS \
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CTX_INCLUDE_EL2_REGS \
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CTX_INCLUDE_NEVE_REGS \
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DEBUG \
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DYN_DISABLE_AUTH \
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EL3_EXCEPTION_HANDLING \
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@ -953,6 +954,7 @@ $(eval $(call add_defines,\
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EL3_EXCEPTION_HANDLING \
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CTX_INCLUDE_MTE_REGS \
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CTX_INCLUDE_EL2_REGS \
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CTX_INCLUDE_NEVE_REGS \
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DECRYPTION_SUPPORT_${DECRYPTION_SUPPORT} \
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ENABLE_AMU \
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ENABLE_ASSERTIONS \
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@ -161,6 +161,10 @@ Common build options
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registers to be included when saving and restoring the CPU context. Default
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is 0.
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- ``CTX_INCLUDE_NEVE_REGS``: Boolean option that, when set to 1, will cause the
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Armv8.4-NV registers to be saved/restored when entering/exiting an EL2
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execution context. Default value is 0.
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- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
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Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
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registers to be included when saving and restoring the CPU context as
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@ -65,9 +65,13 @@ func el2_sysregs_context_save
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mrs x9, cptr_el2
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stp x17, x9, [x0, #CTX_CNTVOFF_EL2]
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mrs x10, dbgvcr32_el2
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mrs x11, elr_el2
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#if CTX_INCLUDE_AARCH32_REGS
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mrs x10, dbgvcr32_el2
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stp x10, x11, [x0, #CTX_DBGVCR32_EL2]
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#else
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str x11, [x0, #CTX_ELR_EL2]
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#endif
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mrs x14, esr_el2
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mrs x15, far_el2
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@ -90,8 +94,12 @@ func el2_sysregs_context_save
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stp x13, x14, [x0, #CTX_ICH_VMCR_EL2]
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mrs x15, mdcr_el2
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#if ENABLE_SPE_FOR_LOWER_ELS
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mrs x16, PMSCR_EL2
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stp x15, x16, [x0, #CTX_MDCR_EL2]
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#else
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str x15, [x0, #CTX_MDCR_EL2]
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#endif
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mrs x17, sctlr_el2
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mrs x9, spsr_el2
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@ -185,8 +193,10 @@ func el2_sysregs_context_save
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mrs x9, contextidr_el2
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stp x17, x9, [x0, #CTX_CNTHV_TVAL_EL2]
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#if CTX_INCLUDE_AARCH32_REGS
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mrs x10, sder32_el2
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str x10, [x0, #CTX_SDER32_EL2]
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#endif
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mrs x11, ttbr1_el2
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str x11, [x0, #CTX_TTBR1_EL2]
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@ -194,8 +204,10 @@ func el2_sysregs_context_save
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mrs x12, vdisr_el2
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str x12, [x0, #CTX_VDISR_EL2]
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#if CTX_INCLUDE_NEVE_REGS
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mrs x13, vncr_el2
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str x13, [x0, #CTX_VNCR_EL2]
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#endif
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mrs x14, vsesr_el2
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str x14, [x0, #CTX_VSESR_EL2]
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@ -255,8 +267,12 @@ func el2_sysregs_context_restore
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msr cntvoff_el2, x17
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msr cptr_el2, x9
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#if CTX_INCLUDE_AARCH32_REGS
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ldp x10, x11, [x0, #CTX_DBGVCR32_EL2]
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msr dbgvcr32_el2, x10
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#else
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ldr x11, [x0, #CTX_ELR_EL2]
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#endif
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msr elr_el2, x11
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ldp x14, x15, [x0, #CTX_ESR_EL2]
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@ -279,9 +295,13 @@ func el2_sysregs_context_restore
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msr ICH_VMCR_EL2, x13
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msr mair_el2, x14
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#if ENABLE_SPE_FOR_LOWER_ELS
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ldp x15, x16, [x0, #CTX_MDCR_EL2]
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msr mdcr_el2, x15
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msr PMSCR_EL2, x16
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#else
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ldr x15, [x0, #CTX_MDCR_EL2]
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#endif
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msr mdcr_el2, x15
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ldp x17, x9, [x0, #CTX_SCTLR_EL2]
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msr sctlr_el2, x17
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@ -374,8 +394,10 @@ func el2_sysregs_context_restore
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msr cnthv_tval_el2, x9
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msr contextidr_el2, x10
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#if CTX_INCLUDE_AARCH32_REGS
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ldr x11, [x0, #CTX_SDER32_EL2]
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msr sder32_el2, x11
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#endif
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ldr x12, [x0, #CTX_TTBR1_EL2]
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msr ttbr1_el2, x12
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@ -383,8 +405,10 @@ func el2_sysregs_context_restore
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ldr x13, [x0, #CTX_VDISR_EL2]
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msr vdisr_el2, x13
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#if CTX_INCLUDE_NEVE_REGS
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ldr x14, [x0, #CTX_VNCR_EL2]
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msr vncr_el2, x14
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#endif
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ldr x15, [x0, #CTX_VSESR_EL2]
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msr vsesr_el2, x15
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@ -62,6 +62,11 @@ CTX_INCLUDE_FPREGS := 0
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# world. It is not needed to use it in the Non-secure world.
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CTX_INCLUDE_PAUTH_REGS := 0
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# Include Nested virtualization control (Armv8.4-NV) registers in cpu context.
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# This must be set to 1 if architecture implements Nested Virtualization
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# Extension and platform wants to use this feature in the Secure world
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CTX_INCLUDE_NEVE_REGS := 0
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# Debug build
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DEBUG := 0
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