xilinx: Add support to send PM API to PMC using IPI for versal
Port ZynqMP PM services for versal to send PM APIs to PMC using IPI. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Wendy Liang <wendy.liang@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I27a52faf27f1a2919213498276a6885a177cb6da
This commit is contained in:
Tejas Patel
Jolly Shah
parent
ab36d09709
commit
c73a90e571
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@ -4,6 +4,7 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat_ipi.h>
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#include <versal_def.h>
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#include <plat_private.h>
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#include <common/debug.h>
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@ -38,6 +39,9 @@ void versal_config_setup(void)
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{
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uint32_t val;
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/* Configure IPI data for versal */
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versal_ipi_config_table_init();
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versal_print_platform_name();
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mmio_write_32(VERSAL_CRL_IOU_SWITCH_CTRL,
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@ -0,0 +1,55 @@
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/*
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* Copyright (c) 2019, Xilinx, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* Versal IPI management enums and defines */
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#ifndef PLAT_IPI_H
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#define PLAT_IPI_H
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#include <ipi.h>
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#include <stdint.h>
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/*********************************************************************
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* IPI agent IDs macros
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********************************************************************/
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#define IPI_ID_PMC 1U
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#define IPI_ID_APU 2U
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#define IPI_ID_RPU0 3U
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#define IPI_ID_RPU1 4U
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#define IPI_ID_3 5U
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#define IPI_ID_4 6U
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#define IPI_ID_5 7U
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/*********************************************************************
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* IPI message buffers
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********************************************************************/
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#define IPI_BUFFER_BASEADDR 0xFF3F0000U
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#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U)
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#define IPI_BUFFER_PMC_BASE (IPI_BUFFER_BASEADDR + 0x200U)
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#define IPI_BUFFER_TARGET_APU_OFFSET 0x0U
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#define IPI_BUFFER_TARGET_PMC_OFFSET 0x40U
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#define IPI_BUFFER_LOCAL_BASE IPI_BUFFER_APU_BASE
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#define IPI_BUFFER_REMOTE_BASE IPI_BUFFER_PMC_BASE
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#define IPI_BUFFER_TARGET_LOCAL_OFFSET IPI_BUFFER_TARGET_APU_OFFSET
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#define IPI_BUFFER_TARGET_REMOTE_OFFSET IPI_BUFFER_TARGET_PMC_OFFSET
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#define IPI_BUFFER_MAX_WORDS 8
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#define IPI_BUFFER_REQ_OFFSET 0x0U
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#define IPI_BUFFER_RESP_OFFSET 0x20U
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/*********************************************************************
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* Platform specific IPI API declarations
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********************************************************************/
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/* Configure IPI table for versal */
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void versal_ipi_config_table_init(void);
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#endif /* PLAT_IPI_H */
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@ -0,0 +1,22 @@
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/*
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* Copyright (c) 2019, Xilinx, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* Contains platform specific definitions of commonly used macros data types
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* for PU Power Management. This file should be common for all PU's.
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*/
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#ifndef PLAT_PM_COMMON_H
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#define PLAT_PM_COMMON_H
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#include <common/debug.h>
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#include <stdint.h>
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#include "pm_defs.h"
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#define PAYLOAD_ARG_CNT 6U
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#define PAYLOAD_ARG_SIZE 4U /* size in bytes */
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#endif /* PLAT_PM_COMMON_H */
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@ -106,4 +106,19 @@
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#define FPD_APU_CONFIG_0_VINITHI_SHIFT 8
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/* IPI registers and bitfields */
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#define IPI0_REG_BASE 0xFF330000
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#define IPI0_TRIG_BIT (1 << 2)
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#define PMC_IPI_TRIG_BIT (1 << 1)
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#define IPI1_REG_BASE 0xFF340000
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#define IPI1_TRIG_BIT (1 << 3)
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#define IPI2_REG_BASE 0xFF350000
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#define IPI2_TRIG_BIT (1 << 4)
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#define IPI3_REG_BASE 0xFF360000
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#define IPI3_TRIG_BIT (1 << 5)
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#define IPI4_REG_BASE 0xFF370000
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#define IPI4_TRIG_BIT (1 << 5)
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#define IPI5_REG_BASE 0xFF380000
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#define IPI5_TRIG_BIT (1 << 6)
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#endif /* VERSAL_DEF_H */
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@ -37,7 +37,9 @@ $(eval $(call add_define_val,VERSAL_PLATFORM,VERSAL_PLATFORM_ID_${VERSAL_PLATFOR
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VERSAL_CONSOLE ?= pl011
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$(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE}))
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PLAT_INCLUDES := -Iplat/xilinx/versal/include/
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PLAT_INCLUDES := -Iplat/xilinx/common/include/ \
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-Iplat/xilinx/versal/include/ \
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-Iplat/xilinx/versal/pm_service/
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PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
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lib/xlat_tables/aarch64/xlat_tables.c \
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@ -55,9 +57,14 @@ PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
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BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a72.S \
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plat/common/plat_psci_common.c \
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plat/xilinx/common/ipi.c \
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plat/xilinx/common/pm_service/pm_ipi.c \
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plat/xilinx/versal/bl31_versal_setup.c \
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plat/xilinx/versal/plat_psci.c \
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plat/xilinx/versal/plat_versal.c \
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plat/xilinx/versal/plat_topology.c \
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plat/xilinx/versal/sip_svc_setup.c \
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plat/xilinx/versal/versal_gicv3.c
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plat/xilinx/versal/versal_gicv3.c \
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plat/xilinx/versal/versal_ipi.c \
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plat/xilinx/versal/pm_service/pm_svc_main.c \
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plat/xilinx/versal/pm_service/pm_client.c
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@ -0,0 +1,38 @@
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/*
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* Copyright (c) 2019, Xilinx, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* APU specific definition of processors in the subsystem as well as functions
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* for getting information about and changing state of the APU.
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*/
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#include <plat_ipi.h>
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#include <platform_def.h>
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#include <versal_def.h>
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#include <lib/bakery_lock.h>
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#include "pm_client.h"
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DEFINE_BAKERY_LOCK(pm_client_secure_lock);
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static const struct pm_ipi apu_ipi = {
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.local_ipi_id = IPI_ID_APU,
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.remote_ipi_id = IPI_ID_PMC,
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.buffer_base = IPI_BUFFER_APU_BASE,
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};
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/* Order in pm_procs_all array must match cpu ids */
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static const struct pm_proc pm_procs_all[] = {
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{
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.node_id = XPM_DEVID_ACPU_0,
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.ipi = &apu_ipi,
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},
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{
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.node_id = XPM_DEVID_ACPU_1,
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.ipi = &apu_ipi,
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}
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};
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const struct pm_proc *primary_proc = &pm_procs_all[0];
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@ -0,0 +1,21 @@
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/*
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* Copyright (c) 2019, Xilinx, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* Contains APU specific macros and macros to be defined depending on
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* the execution environment.
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*/
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#ifndef PM_CLIENT_H
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#define PM_CLIENT_H
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#include "pm_common.h"
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#include "pm_defs.h"
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/* Global variables to be set in pm_client.c */
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extern const struct pm_proc *primary_proc;
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#endif /* PM_CLIENT_H */
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@ -0,0 +1,55 @@
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/*
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* Copyright (c) 2019, Xilinx, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* Versal power management enums and defines */
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#ifndef PM_DEFS_H
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#define PM_DEFS_H
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#include "pm_node.h"
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/*********************************************************************
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* Macro definitions
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********************************************************************/
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/* Processor core device IDs */
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#define APU_DEVID(IDX) NODEID(XPM_NODECLASS_DEVICE, XPM_NODESUBCL_DEV_CORE, \
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XPM_NODETYPE_DEV_CORE_APU, (IDX))
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#define XPM_DEVID_ACPU_0 APU_DEVID(XPM_NODEIDX_DEV_ACPU_0)
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#define XPM_DEVID_ACPU_1 APU_DEVID(XPM_NODEIDX_DEV_ACPU_1)
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/*********************************************************************
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* Enum definitions
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********************************************************************/
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/**
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* @PM_RET_SUCCESS: success
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* @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated)
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* @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated)
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* @PM_RET_ERROR_INTERNAL: internal error
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* @PM_RET_ERROR_CONFLICT: conflict
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* @PM_RET_ERROR_ACCESS: access rights violation
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* @PM_RET_ERROR_INVALID_NODE: invalid node
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* @PM_RET_ERROR_DOUBLE_REQ: duplicate request for same node
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* @PM_RET_ERROR_ABORT_SUSPEND: suspend procedure has been aborted
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* @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU
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* @PM_RET_ERROR_NODE_USED: node is already in use
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*/
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enum pm_ret_status {
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PM_RET_SUCCESS,
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PM_RET_ERROR_ARGS = 1,
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PM_RET_ERROR_NOTSUPPORTED = 4,
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PM_RET_ERROR_INTERNAL = 2000,
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PM_RET_ERROR_CONFLICT = 2001,
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PM_RET_ERROR_ACCESS = 2002,
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PM_RET_ERROR_INVALID_NODE = 2003,
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PM_RET_ERROR_DOUBLE_REQ = 2004,
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PM_RET_ERROR_ABORT_SUSPEND = 2005,
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PM_RET_ERROR_TIMEOUT = 2006,
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PM_RET_ERROR_NODE_USED = 2007
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};
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#endif /* PM_DEFS_H */
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@ -0,0 +1,192 @@
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/*
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* Copyright (c) 2019, Xilinx, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* Versal PM nodes enums and defines */
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#ifndef PM_NODE_H
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#define PM_NODE_H
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/*********************************************************************
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* Macro definitions
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********************************************************************/
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#define NODE_CLASS_SHIFT 26U
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#define NODE_SUBCLASS_SHIFT 20U
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#define NODE_TYPE_SHIFT 14U
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#define NODE_INDEX_SHIFT 0U
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#define NODE_CLASS_MASK_BITS 0x3F
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#define NODE_SUBCLASS_MASK_BITS 0x3F
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#define NODE_TYPE_MASK_BITS 0x3F
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#define NODE_INDEX_MASK_BITS 0x3FFF
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#define NODE_CLASS_MASK (NODE_CLASS_MASK_BITS << NODE_CLASS_SHIFT)
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#define NODE_SUBCLASS_MASK (NODE_SUBCLASS_MASK_BITS << NODE_SUBCLASS_SHIFT)
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#define NODE_TYPE_MASK (NODE_TYPE_MASK_BITS << NODE_TYPE_SHIFT)
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#define NODE_INDEX_MASK (NODE_INDEX_MASK_BITS << NODE_INDEX_SHIFT)
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#define NODEID(CLASS, SUBCLASS, TYPE, INDEX) \
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((((CLASS) & NODE_CLASS_MASK_BITS) << NODE_CLASS_SHIFT) | \
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(((SUBCLASS) & NODE_SUBCLASS_MASK_BITS) << NODE_SUBCLASS_SHIFT) | \
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(((TYPE) & NODE_TYPE_MASK_BITS) << NODE_TYPE_SHIFT) | \
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(((INDEX) & NODE_INDEX_MASK_BITS) << NODE_INDEX_SHIFT))
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#define NODECLASS(ID) (((ID) & NODE_CLASS_MASK) >> NODE_CLASS_SHIFT)
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#define NODESUBCLASS(ID) (((ID) & NODE_SUBCLASS_MASK) >> \
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NODE_SUBCLASS_SHIFT)
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#define NODETYPE(ID) (((ID) & NODE_TYPE_MASK) >> NODE_TYPE_SHIFT)
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#define NODEINDEX(ID) (((ID) & NODE_INDEX_MASK) >> NODE_INDEX_SHIFT)
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/*********************************************************************
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* Enum definitions
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********************************************************************/
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/* Node class types */
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enum pm_node_class {
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XPM_NODECLASS_MIN,
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XPM_NODECLASS_POWER,
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XPM_NODECLASS_CLOCK,
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XPM_NODECLASS_RESET,
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XPM_NODECLASS_MEMIC,
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XPM_NODECLASS_STMIC,
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XPM_NODECLASS_DEVICE,
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XPM_NODECLASS_MAX
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};
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enum pm_device_node_subclass {
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/* Device types */
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XPM_NODESUBCL_DEV_CORE = 1,
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XPM_NODESUBCL_DEV_PERIPH,
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XPM_NODESUBCL_DEV_MEM,
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XPM_NODESUBCL_DEV_SOC,
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XPM_NODESUBCL_DEV_MEM_CTRLR,
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XPM_NODESUBCL_DEV_PHY,
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};
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enum pm_device_node_type {
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/* Device types */
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XPM_NODETYPE_DEV_CORE_PMC = 1,
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XPM_NODETYPE_DEV_CORE_PSM,
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XPM_NODETYPE_DEV_CORE_APU,
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XPM_NODETYPE_DEV_CORE_RPU,
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XPM_NODETYPE_DEV_OCM,
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XPM_NODETYPE_DEV_TCM,
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XPM_NODETYPE_DEV_L2CACHE,
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XPM_NODETYPE_DEV_DDR,
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XPM_NODETYPE_DEV_PERIPH,
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XPM_NODETYPE_DEV_SOC,
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XPM_NODETYPE_DEV_GT,
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};
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/* Device node Indexes */
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enum pm_device_node_idx {
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/* Device nodes */
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XPM_NODEIDX_DEV_MIN,
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/* Processor devices */
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XPM_NODEIDX_DEV_PMC_PROC,
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XPM_NODEIDX_DEV_PSM_PROC,
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XPM_NODEIDX_DEV_ACPU_0,
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XPM_NODEIDX_DEV_ACPU_1,
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XPM_NODEIDX_DEV_RPU0_0,
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XPM_NODEIDX_DEV_RPU0_1,
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/* Memory devices */
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XPM_NODEIDX_DEV_OCM_0,
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XPM_NODEIDX_DEV_OCM_1,
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XPM_NODEIDX_DEV_OCM_2,
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XPM_NODEIDX_DEV_OCM_3,
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XPM_NODEIDX_DEV_TCM_0_A,
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XPM_NODEIDX_DEV_TCM_0_B,
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XPM_NODEIDX_DEV_TCM_1_A,
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XPM_NODEIDX_DEV_TCM_1_B,
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XPM_NODEIDX_DEV_L2_BANK_0,
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XPM_NODEIDX_DEV_DDR_0,
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XPM_NODEIDX_DEV_DDR_1,
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XPM_NODEIDX_DEV_DDR_2,
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XPM_NODEIDX_DEV_DDR_3,
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XPM_NODEIDX_DEV_DDR_4,
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XPM_NODEIDX_DEV_DDR_5,
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XPM_NODEIDX_DEV_DDR_6,
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XPM_NODEIDX_DEV_DDR_7,
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/* LPD Peripheral devices */
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XPM_NODEIDX_DEV_USB_0,
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XPM_NODEIDX_DEV_GEM_0,
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XPM_NODEIDX_DEV_GEM_1,
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XPM_NODEIDX_DEV_SPI_0,
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XPM_NODEIDX_DEV_SPI_1,
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XPM_NODEIDX_DEV_I2C_0,
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XPM_NODEIDX_DEV_I2C_1,
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XPM_NODEIDX_DEV_CAN_FD_0,
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XPM_NODEIDX_DEV_CAN_FD_1,
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XPM_NODEIDX_DEV_UART_0,
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XPM_NODEIDX_DEV_UART_1,
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XPM_NODEIDX_DEV_GPIO,
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XPM_NODEIDX_DEV_TTC_0,
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XPM_NODEIDX_DEV_TTC_1,
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XPM_NODEIDX_DEV_TTC_2,
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XPM_NODEIDX_DEV_TTC_3,
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XPM_NODEIDX_DEV_SWDT_LPD,
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/* FPD Peripheral devices */
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XPM_NODEIDX_DEV_SWDT_FPD,
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/* PMC Peripheral devices */
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XPM_NODEIDX_DEV_OSPI,
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XPM_NODEIDX_DEV_QSPI,
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XPM_NODEIDX_DEV_GPIO_PMC,
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XPM_NODEIDX_DEV_I2C_PMC,
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XPM_NODEIDX_DEV_SDIO_0,
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XPM_NODEIDX_DEV_SDIO_1,
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XPM_NODEIDX_DEV_PL_0,
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XPM_NODEIDX_DEV_PL_1,
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XPM_NODEIDX_DEV_PL_2,
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XPM_NODEIDX_DEV_PL_3,
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XPM_NODEIDX_DEV_RTC,
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XPM_NODEIDX_DEV_ADMA_0,
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XPM_NODEIDX_DEV_ADMA_1,
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XPM_NODEIDX_DEV_ADMA_2,
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XPM_NODEIDX_DEV_ADMA_3,
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XPM_NODEIDX_DEV_ADMA_4,
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XPM_NODEIDX_DEV_ADMA_5,
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XPM_NODEIDX_DEV_ADMA_6,
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XPM_NODEIDX_DEV_ADMA_7,
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XPM_NODEIDX_DEV_IPI_0,
|
||||
XPM_NODEIDX_DEV_IPI_1,
|
||||
XPM_NODEIDX_DEV_IPI_2,
|
||||
XPM_NODEIDX_DEV_IPI_3,
|
||||
XPM_NODEIDX_DEV_IPI_4,
|
||||
XPM_NODEIDX_DEV_IPI_5,
|
||||
XPM_NODEIDX_DEV_IPI_6,
|
||||
|
||||
/* Entire SoC */
|
||||
XPM_NODEIDX_DEV_SOC,
|
||||
|
||||
/* DDR memory controllers */
|
||||
XPM_NODEIDX_DEV_DDRMC_0,
|
||||
XPM_NODEIDX_DEV_DDRMC_1,
|
||||
XPM_NODEIDX_DEV_DDRMC_2,
|
||||
XPM_NODEIDX_DEV_DDRMC_3,
|
||||
|
||||
/* GT devices */
|
||||
XPM_NODEIDX_DEV_GT_0,
|
||||
XPM_NODEIDX_DEV_GT_1,
|
||||
XPM_NODEIDX_DEV_GT_2,
|
||||
XPM_NODEIDX_DEV_GT_3,
|
||||
XPM_NODEIDX_DEV_GT_4,
|
||||
XPM_NODEIDX_DEV_GT_5,
|
||||
XPM_NODEIDX_DEV_GT_6,
|
||||
XPM_NODEIDX_DEV_GT_7,
|
||||
XPM_NODEIDX_DEV_GT_8,
|
||||
XPM_NODEIDX_DEV_GT_9,
|
||||
XPM_NODEIDX_DEV_GT_10,
|
||||
|
||||
XPM_NODEIDX_DEV_MAX
|
||||
};
|
||||
|
||||
#endif /* PM_NODE_H */
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* Top-level SMC handler for Versal power management calls and
|
||||
* IPI setup functions for communication with PMC.
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
#include <plat_private.h>
|
||||
#include "pm_client.h"
|
||||
#include "pm_ipi.h"
|
||||
|
||||
/**
|
||||
* pm_setup() - PM service setup
|
||||
*
|
||||
* @return On success, the initialization function must return 0.
|
||||
* Any other return value will cause the framework to ignore
|
||||
* the service
|
||||
*
|
||||
* Initialization functions for Versal power management for
|
||||
* communicaton with PMC.
|
||||
*
|
||||
* Called from sip_svc_setup initialization function with the
|
||||
* rt_svc_init signature.
|
||||
*/
|
||||
int pm_setup(void)
|
||||
{
|
||||
int status, ret = 0;
|
||||
|
||||
status = pm_ipi_init(primary_proc);
|
||||
|
||||
if (status < 0) {
|
||||
INFO("BL31: PM Service Init Failed, Error Code %d!\n", status);
|
||||
ret = status;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PM_SVC_MAIN_H
|
||||
#define PM_SVC_MAIN_H
|
||||
|
||||
#include <pm_common.h>
|
||||
|
||||
int pm_setup(void);
|
||||
|
||||
#endif /* PM_SVC_MAIN_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -9,6 +9,7 @@
|
|||
#include <common/debug.h>
|
||||
#include <common/runtime_svc.h>
|
||||
#include <tools_share/uuid.h>
|
||||
#include "pm_svc_main.h"
|
||||
|
||||
/* SMC function IDs for SiP Service queries */
|
||||
#define VERSAL_SIP_SVC_CALL_COUNT 0x8200ff00
|
||||
|
|
@ -36,6 +37,9 @@ DEFINE_SVC_UUID2(versal_sip_uuid,
|
|||
*/
|
||||
static int32_t sip_svc_setup(void)
|
||||
{
|
||||
/* PM implementation as SiP Service */
|
||||
pm_setup();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* Versal IPI agent registers access management
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
#include <ipi.h>
|
||||
#include <plat_ipi.h>
|
||||
#include <plat_private.h>
|
||||
#include <string.h>
|
||||
#include <common/debug.h>
|
||||
#include <common/runtime_svc.h>
|
||||
#include <lib/bakery_lock.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
/* versal ipi configuration table */
|
||||
const static struct ipi_config versal_ipi_table[] = {
|
||||
/* A72 IPI */
|
||||
[IPI_ID_APU] = {
|
||||
.ipi_bit_mask = IPI0_TRIG_BIT,
|
||||
.ipi_reg_base = IPI0_REG_BASE,
|
||||
.secure_only = 0,
|
||||
},
|
||||
|
||||
/* PMC IPI */
|
||||
[IPI_ID_PMC] = {
|
||||
.ipi_bit_mask = PMC_IPI_TRIG_BIT,
|
||||
.ipi_reg_base = IPI0_REG_BASE,
|
||||
.secure_only = 0,
|
||||
},
|
||||
|
||||
/* RPU0 IPI */
|
||||
[IPI_ID_RPU0] = {
|
||||
.ipi_bit_mask = IPI1_TRIG_BIT,
|
||||
.ipi_reg_base = IPI1_REG_BASE,
|
||||
.secure_only = 0,
|
||||
},
|
||||
|
||||
/* RPU1 IPI */
|
||||
[IPI_ID_RPU1] = {
|
||||
.ipi_bit_mask = IPI2_TRIG_BIT,
|
||||
.ipi_reg_base = IPI2_REG_BASE,
|
||||
.secure_only = 0,
|
||||
},
|
||||
|
||||
/* IPI3 IPI */
|
||||
[IPI_ID_3] = {
|
||||
.ipi_bit_mask = IPI3_TRIG_BIT,
|
||||
.ipi_reg_base = IPI3_REG_BASE,
|
||||
.secure_only = 0,
|
||||
},
|
||||
|
||||
/* IPI4 IPI */
|
||||
[IPI_ID_4] = {
|
||||
.ipi_bit_mask = IPI4_TRIG_BIT,
|
||||
.ipi_reg_base = IPI4_REG_BASE,
|
||||
.secure_only = 0,
|
||||
},
|
||||
|
||||
/* IPI5 IPI */
|
||||
[IPI_ID_5] = {
|
||||
.ipi_bit_mask = IPI5_TRIG_BIT,
|
||||
.ipi_reg_base = IPI5_REG_BASE,
|
||||
.secure_only = 0,
|
||||
},
|
||||
};
|
||||
|
||||
/* versal_ipi_config_table_init() - Initialize versal IPI configuration data
|
||||
*
|
||||
* @ipi_config_table - IPI configuration table
|
||||
* @ipi_total - Total number of IPI available
|
||||
*
|
||||
*/
|
||||
void versal_ipi_config_table_init(void)
|
||||
{
|
||||
ipi_config_table_init(versal_ipi_table, ARRAY_SIZE(versal_ipi_table));
|
||||
}
|
||||
Loading…
Reference in New Issue