Merge changes Ib68092d1,I816ea14e into integration
* changes: plat: marvell: armada: scp_bl2: allow loading up to 8 images plat: marvell: armada: add support for loading MG CM3 images
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commit
c83d66ec63
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@ -303,7 +303,7 @@ static void cp110_axi_attr_init(uintptr_t base)
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DOMAIN_SYSTEM_SHAREABLE);
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DOMAIN_SYSTEM_SHAREABLE);
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}
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}
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static void amb_bridge_init(uintptr_t base)
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void cp110_amb_init(uintptr_t base)
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{
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{
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uint32_t reg;
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uint32_t reg;
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@ -399,7 +399,7 @@ void cp110_init(uintptr_t cp110_base, uint32_t stream_id)
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cp110_stream_id_init(cp110_base, stream_id);
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cp110_stream_id_init(cp110_base, stream_id);
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/* Open AMB bridge for comphy for CP0 & CP1*/
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/* Open AMB bridge for comphy for CP0 & CP1*/
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amb_bridge_init(cp110_base);
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cp110_amb_init(cp110_base);
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/* Reset RTC if needed */
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/* Reset RTC if needed */
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cp110_rtc_init(cp110_base);
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cp110_rtc_init(cp110_base);
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@ -411,7 +411,7 @@ void cp110_ble_init(uintptr_t cp110_base)
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#if PCI_EP_SUPPORT
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#if PCI_EP_SUPPORT
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INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base);
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INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base);
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amb_bridge_init(cp110_base);
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cp110_amb_init(cp110_base);
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/* Configure PCIe clock */
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/* Configure PCIe clock */
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cp110_pcie_clk_cfg(cp110_base);
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cp110_pcie_clk_cfg(cp110_base);
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@ -51,5 +51,6 @@ static inline uint32_t cp110_rev_id_get(uintptr_t base)
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void cp110_init(uintptr_t cp110_base, uint32_t stream_id);
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void cp110_init(uintptr_t cp110_base, uint32_t stream_id);
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void cp110_ble_init(uintptr_t cp110_base);
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void cp110_ble_init(uintptr_t cp110_base);
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void cp110_amb_init(uintptr_t base);
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#endif /* CP110_SETUP_H */
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#endif /* CP110_SETUP_H */
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@ -8,7 +8,8 @@
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PLAT_MARVELL := plat/marvell
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PLAT_MARVELL := plat/marvell
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A8K_MSS_SOURCE := $(PLAT_MARVELL)/a8k/common/mss
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A8K_MSS_SOURCE := $(PLAT_MARVELL)/a8k/common/mss
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BL2_SOURCES += $(A8K_MSS_SOURCE)/mss_bl2_setup.c
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BL2_SOURCES += $(A8K_MSS_SOURCE)/mss_bl2_setup.c \
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$(MARVELL_MOCHI_DRV)
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BL31_SOURCES += $(A8K_MSS_SOURCE)/mss_pm_ipc.c
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BL31_SOURCES += $(A8K_MSS_SOURCE)/mss_pm_ipc.c
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@ -74,6 +74,12 @@ static int bl2_plat_mmap_init(void)
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/* Set the default target id to PIDI */
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/* Set the default target id to PIDI */
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mmio_write_32(MVEBU_IO_WIN_BASE(MVEBU_AP0) + IOW_GCR_OFFSET, PIDI_TID);
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mmio_write_32(MVEBU_IO_WIN_BASE(MVEBU_AP0) + IOW_GCR_OFFSET, PIDI_TID);
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/* Open AMB bridge required for MG access */
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cp110_amb_init(MVEBU_CP_REGS_BASE(0));
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if (CP_COUNT == 2)
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cp110_amb_init(MVEBU_CP_REGS_BASE(1));
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return 0;
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return 0;
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}
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}
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@ -8,7 +8,7 @@
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#ifndef MSS_SCP_BL2_FORMAT_H
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#ifndef MSS_SCP_BL2_FORMAT_H
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#define MSS_SCP_BL2_FORMAT_H
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#define MSS_SCP_BL2_FORMAT_H
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#define MAX_NR_OF_FILES 5
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#define MAX_NR_OF_FILES 8
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#define FILE_MAGIC 0xddd01ff
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#define FILE_MAGIC 0xddd01ff
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#define HEADER_VERSION 0x1
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#define HEADER_VERSION 0x1
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@ -31,6 +31,7 @@ enum cm3_t {
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MSS_CP3,
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MSS_CP3,
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MG_CP0,
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MG_CP0,
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MG_CP1,
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MG_CP1,
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MG_CP2,
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};
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};
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typedef struct img_header {
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typedef struct img_header {
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@ -42,6 +42,8 @@
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#define MSS_HANDSHAKE_TIMEOUT 50
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#define MSS_HANDSHAKE_TIMEOUT 50
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#define MG_CM3_SRAM_BASE(CP) (MVEBU_CP_REGS_BASE(CP) + 0x100000)
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static int mss_check_image_ready(volatile struct mss_pm_ctrl_block *mss_pm_crtl)
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static int mss_check_image_ready(volatile struct mss_pm_ctrl_block *mss_pm_crtl)
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{
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{
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int timeout = MSS_HANDSHAKE_TIMEOUT;
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int timeout = MSS_HANDSHAKE_TIMEOUT;
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@ -59,6 +61,28 @@ static int mss_check_image_ready(volatile struct mss_pm_ctrl_block *mss_pm_crtl)
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return 0;
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return 0;
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}
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}
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static int mg_image_load(uintptr_t src_addr, uint32_t size, uintptr_t mg_regs)
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{
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if (size > MG_SRAM_SIZE) {
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ERROR("image is too big to fit into MG CM3 memory\n");
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return 1;
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}
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NOTICE("Loading MG image from address 0x%lx Size 0x%x to MG at 0x%lx\n",
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src_addr, size, mg_regs);
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/* Copy image to MG CM3 SRAM */
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memcpy((void *)mg_regs, (void *)src_addr, size);
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/*
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* Don't release MG CM3 from reset - it will be done by next step
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* bootloader (e.g. U-Boot), when appriopriate device-tree setup (which
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* has enabeld 802.3. auto-neg) will be choosen.
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*/
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return 0;
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}
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static int mss_image_load(uint32_t src_addr, uint32_t size, uintptr_t mss_regs)
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static int mss_image_load(uint32_t src_addr, uint32_t size, uintptr_t mss_regs)
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{
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{
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uint32_t i, loop_num, timeout;
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uint32_t i, loop_num, timeout;
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@ -225,12 +249,21 @@ static int load_img_to_cm3(enum cm3_t cm3_type,
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}
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}
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break;
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break;
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case MG_CP0:
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case MG_CP0:
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/* TODO: */
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NOTICE("Load image to CP0 MG not supported\n");
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break;
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case MG_CP1:
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case MG_CP1:
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/* TODO: */
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case MG_CP2:
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NOTICE("Load image to CP1 MG not supported\n");
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cp_index = cm3_type - MG_CP0;
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if (bl2_plat_get_cp_count(0) <= cp_index) {
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NOTICE("Skipping MG CP%d related image\n",
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cp_index);
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break;
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}
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NOTICE("Load image to CP%d MG\n", cp_index);
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ret = mg_image_load(single_img, image_size,
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MG_CM3_SRAM_BASE(cp_index));
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if (ret != 0) {
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ERROR("SCP Image load failed\n");
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return -1;
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}
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break;
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break;
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default:
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default:
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ERROR("SCP_BL2 wrong img format (cm3_type=%d)\n", cm3_type);
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ERROR("SCP_BL2 wrong img format (cm3_type=%d)\n", cm3_type);
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@ -261,7 +294,7 @@ static int split_and_load_bl2_image(void *image)
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}
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}
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if (file_hdr->nr_of_imgs > MAX_NR_OF_FILES) {
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if (file_hdr->nr_of_imgs > MAX_NR_OF_FILES) {
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ERROR("SCP_BL2 concatenated image contains to many images\n");
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ERROR("SCP_BL2 concatenated image contains too many images\n");
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return -1;
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return -1;
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}
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}
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