Introduce locking primitives using CAS instruction
The ARMv8v.1 architecture extension has introduced support for far
atomics, which includes compare-and-swap. Compare and Swap instruction
is only available for AArch64.
Introduce build options to choose the architecture versions to target
ARM Trusted Firmware:
- ARM_ARCH_MAJOR: selects the major version of target ARM
Architecture. Default value is 8.
- ARM_ARCH_MINOR: selects the minor version of target ARM
Architecture. Default value is 0.
When:
(ARM_ARCH_MAJOR > 8) || ((ARM_ARCH_MAJOR == 8) && (ARM_ARCH_MINOR >= 1)),
for AArch64, Compare and Swap instruction is used to implement spin
locks. Otherwise, the implementation falls back to using
load-/store-exclusive instructions.
Update user guide, and introduce a section in Firmware Design guide to
summarize support for features introduced in ARMv8 Architecture
Extensions.
Change-Id: I73096a0039502f7aef9ec6ab3ae36680da033f16
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
This commit is contained in:
Jeenu Viswambharan
parent
4d07e7821e
commit
c877b41487
5
Makefile
5
Makefile
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@ -397,6 +397,9 @@ $(eval $(call assert_boolean,SPIN_ON_BL1_EXIT))
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$(eval $(call assert_boolean,TRUSTED_BOARD_BOOT))
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$(eval $(call assert_boolean,USE_COHERENT_MEM))
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$(eval $(call assert_numeric,ARM_ARCH_MAJOR))
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$(eval $(call assert_numeric,ARM_ARCH_MINOR))
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################################################################################
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# Add definitions to the cpp preprocessor based on the current build options.
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# This is done after including the platform specific makefile to allow the
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@ -404,6 +407,8 @@ $(eval $(call assert_boolean,USE_COHERENT_MEM))
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################################################################################
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$(eval $(call add_define,ARM_CCI_PRODUCT_ID))
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$(eval $(call add_define,ARM_ARCH_MAJOR))
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$(eval $(call add_define,ARM_ARCH_MINOR))
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$(eval $(call add_define,ARM_GIC_ARCH))
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$(eval $(call add_define,ASM_ASSERTION))
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$(eval $(call add_define,COLD_BOOT_SINGLE_CPU))
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@ -16,8 +16,9 @@ Contents :
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11. [Use of coherent memory in Trusted Firmware](#11--use-of-coherent-memory-in-trusted-firmware)
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12. [Isolating code and read-only data on separate memory pages](#12--isolating-code-and-read-only-data-on-separate-memory-pages)
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13. [Performance Measurement Framework](#13--performance-measurement-framework)
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14. [Code Structure](#14--code-structure)
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15. [References](#15--references)
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14. [ARMv8 Architecture Extensions](#14--armv8-architecture-extensions)
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15. [Code Structure](#15--code-structure)
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16. [References](#16--references)
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1. Introduction
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@ -2208,7 +2209,39 @@ in this implementation.
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5. `pmf_helpers.h` is an internal header used by `pmf.h`.
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14. Code Structure
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14. ARMv8 Architecture Extensions
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----------------------------------
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ARM Trusted Firmware makes use of ARMv8 Architecture Extensions where
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applicable. This section lists the usage of Architecture Extensions, and build
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flags controlling them.
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In general, and unless individually mentioned, the build options
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`ARM_ARCH_MAJOR` and `ARM_ARCH_MINOR` selects the Architecture Extension to
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target when building ARM Trusted Firmware. Subsequent ARM Architecture
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Extensions are backward compatible with previous versions.
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The build system only requires that `ARM_ARCH_MAJOR` and `ARM_ARCH_MINOR` have a
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valid numeric value. These build options only control whether or not
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Architecture Extension-specific code is included in the build. Otherwise, ARM
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Trusted Firmware targets the base ARMv8.0 architecture; i.e. as if
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`ARM_ARCH_MAJOR` == 8 and `ARM_ARCH_MINOR` == 0, which are also their respective
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default values.
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See also the _Summary of build options_ in [User Guide].
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For details on the Architecture Extension and available features, please refer
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to the respective Architecture Extension Supplement.
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### ARMv8.1
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This Architecture Extension is targeted when `ARM_ARCH_MAJOR` >= 8, or when
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`ARM_ARCH_MAJOR` == 8 and `ARM_ARCH_MINOR` >= 1.
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* The Compare and Swap instruction is used to implement spinlocks. Otherwise,
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the load-/store-exclusive instruction pair is used.
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15. Code Structure
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-------------------
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Trusted Firmware code is logically divided between the three boot loader
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@ -2252,7 +2285,7 @@ FDTs provide a description of the hardware platform and are used by the Linux
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kernel at boot time. These can be found in the `fdts` directory.
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15. References
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16. References
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---------------
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1. Trusted Board Boot Requirements CLIENT PDD (ARM DEN 0006B-5). Available
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@ -181,6 +181,14 @@ performed.
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is used to determine the number of valid slave interfaces available in the
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ARM CCI driver. Default is 400 (that is, CCI-400).
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* `ARM_ARCH_MAJOR`: The major version of ARM Architecture to target when
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compiling ARM Trusted Firmware. Its value must be numeric, and defaults to
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8. See also, _ARMv8 Architecture Extensions_ in [Firmware Design].
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* `ARM_ARCH_MINOR`: The minor version of ARM Architecture to target when
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compiling ARM Trusted Firmware. Its value must be a numeric, and defaults
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to 0. See also, _ARMv8 Architecture Extensions_ in [Firmware Design].
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* `ARM_GIC_ARCH`: Choice of ARM GIC architecture version used by the ARM
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Legacy GIC driver for implementing the platform GIC API. This API is used
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by the interrupt management framework. Default is 2 (that is, version 2.0).
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -33,7 +33,66 @@
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.globl spin_lock
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.globl spin_unlock
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#if (ARM_ARCH_MAJOR > 8) || ((ARM_ARCH_MAJOR == 8) && (ARM_ARCH_MINOR >= 1))
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/*
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* When compiled for ARMv8.1 or later, choose spin locks based on Compare and
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* Swap instruction.
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*/
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# define USE_CAS 1
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/*
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* Lock contenders using CAS, upon failing to acquire the lock, wait with the
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* monitor in open state. Therefore, a normal store upon unlocking won't
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* generate an SEV. Use explicit SEV instruction with CAS unlock.
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*/
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# define COND_SEV() sev
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#else
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# define USE_CAS 0
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/*
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* Lock contenders using exclusive pairs, upon failing to acquire the lock, wait
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* with the monitor in exclusive state. A normal store upon unlocking will
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* implicitly generate an envent; so, no explicit SEV with unlock is required.
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*/
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# define COND_SEV()
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#endif
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#if USE_CAS
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.arch armv8.1-a
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/*
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* Acquire lock using Compare and Swap instruction.
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*
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* Compare for 0 with acquire semantics, and swap 1. Wait until CAS returns
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* 0.
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*
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* void spin_lock(spinlock_t *lock);
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*/
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func spin_lock
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mov w2, #1
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sevl
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1:
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wfe
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mov w1, wzr
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casa w1, w2, [x0]
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cbnz w1, 1b
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ret
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endfunc spin_lock
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.arch armv8-a
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#else /* !USE_CAS */
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/*
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* Acquire lock using load-/store-exclusive instruction pair.
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*
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* void spin_lock(spinlock_t *lock);
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*/
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func spin_lock
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mov w2, #1
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sevl
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@ -45,8 +104,17 @@ l2: ldaxr w1, [x0]
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ret
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endfunc spin_lock
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#endif /* USE_CAS */
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/*
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* Release lock previously acquired by spin_lock.
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*
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* Unconditionally write 0, and conditionally generate an event.
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*
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* void spin_unlock(spinlock_t *lock);
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*/
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func spin_unlock
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stlr wzr, [x0]
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COND_SEV()
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ret
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endfunc spin_unlock
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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@ -81,6 +81,16 @@ define assert_boolean
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$(and $(patsubst 0,,$(value $(1))),$(patsubst 1,,$(value $(1))),$(error $(1) must be boolean))
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endef
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0-9 := 0 1 2 3 4 5 6 7 8 9
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# Function to verify that a given option $(1) contains a numeric value
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define assert_numeric
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$(if $($(1)),,$(error $(1) must not be empty))
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$(eval __numeric := $($(1)))
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$(foreach d,$(0-9),$(eval __numeric := $(subst $(d),,$(__numeric))))
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$(if $(__numeric),$(error $(1) must be numeric))
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endef
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# IMG_LINKERFILE defines the linker script corresponding to a BL stage
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# $(1) = BL stage (2, 30, 31, 32, 33)
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define IMG_LINKERFILE
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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@ -44,6 +44,10 @@ ARCH := aarch64
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# port can change this value if needed.
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ARM_CCI_PRODUCT_ID := 400
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# ARM Architecture major and minor versions: 8.0 by default.
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ARM_ARCH_MAJOR := 8
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ARM_ARCH_MINOR := 0
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# Determine the version of ARM GIC architecture to use for interrupt management
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# in EL3. The platform port can change this value if needed.
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ARM_GIC_ARCH := 2
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