Tegra: introduce delay timer support
This patch introduces the backend required for implementing the delay timer API. Tegra has an on-chip free flowing us timer which can be used as the delay timer. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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c896132679
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@ -161,6 +161,11 @@ void bl31_platform_setup(void)
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{
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{
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uint32_t tmp_reg;
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uint32_t tmp_reg;
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/*
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* Initialize delay timer
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*/
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tegra_delay_timer_init();
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/*
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/*
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* Setup secondary CPU POR infrastructure.
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* Setup secondary CPU POR infrastructure.
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*/
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*/
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@ -48,6 +48,7 @@ COMMON_DIR := plat/nvidia/tegra/common
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BL31_SOURCES += drivers/arm/gic/gic_v2.c \
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BL31_SOURCES += drivers/arm/gic/gic_v2.c \
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drivers/arm/gic/gic_v3.c \
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drivers/arm/gic/gic_v3.c \
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drivers/console/console.S \
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drivers/console/console.S \
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drivers/delay_timer/delay_timer.c \
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drivers/ti/uart/16550_console.S \
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drivers/ti/uart/16550_console.S \
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lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a57.S \
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lib/cpus/aarch64/cortex_a57.S \
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@ -57,6 +58,7 @@ BL31_SOURCES += drivers/arm/gic/gic_v2.c \
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${COMMON_DIR}/drivers/pmc/pmc.c \
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${COMMON_DIR}/drivers/pmc/pmc.c \
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${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
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${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
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${COMMON_DIR}/tegra_bl31_setup.c \
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${COMMON_DIR}/tegra_bl31_setup.c \
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${COMMON_DIR}/tegra_delay_timer.c \
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${COMMON_DIR}/tegra_gic.c \
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${COMMON_DIR}/tegra_gic.c \
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${COMMON_DIR}/tegra_pm.c \
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${COMMON_DIR}/tegra_pm.c \
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${COMMON_DIR}/tegra_sip_calls.c \
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${COMMON_DIR}/tegra_sip_calls.c \
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@ -0,0 +1,53 @@
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <delay_timer.h>
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#include <mmio.h>
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#include <tegra_def.h>
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static uint32_t tegra_timerus_get_value(void)
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{
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return mmio_read_32(TEGRA_TMRUS_BASE);
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}
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static const timer_ops_t tegra_timer_ops = {
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.get_timer_value = tegra_timerus_get_value,
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.clk_mult = 1,
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.clk_div = 1,
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};
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/*
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* Initialise the on-chip free rolling us counter as the delay
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* timer.
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*/
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void tegra_delay_timer_init(void)
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{
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timer_init(&tegra_timer_ops);
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}
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@ -74,4 +74,7 @@ int tegra_prepare_cpu_on_finish(unsigned long mpidr);
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plat_params_from_bl2_t *bl31_get_plat_params(void);
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plat_params_from_bl2_t *bl31_get_plat_params(void);
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int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes);
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int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes);
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/* Declarations for tegra_delay_timer.c */
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void tegra_delay_timer_init(void);
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#endif /* __TEGRA_PRIVATE_H__ */
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#endif /* __TEGRA_PRIVATE_H__ */
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