From 7b76c20d8eb4271b381371ce0d510fbe6ad825bf Mon Sep 17 00:00:00 2001 From: Okash Khawaja Date: Thu, 21 Apr 2022 12:20:21 +0100 Subject: [PATCH] fix(errata): workarounds for cortex-x1 errata This patch adds workarounds for following cortex-x1 errata: - 1821534 (CatB) - 1688305 (CatB) - 1827429 (CatB) SDEN can be found here: https://developer.arm.com/documentation/SDEN1401782/latest Signed-off-by: Okash Khawaja Change-Id: I10ebe8d5c56a6d273820bb2c682f21bf98daa7a5 --- docs/design/cpu-specific-build-macros.rst | 11 ++ include/lib/cpus/aarch64/cortex_x1.h | 5 + lib/cpus/aarch64/cortex_x1.S | 124 +++++++++++++++++++++- lib/cpus/cpu-ops.mk | 24 +++++ 4 files changed, 163 insertions(+), 1 deletion(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 11419be02..771700c11 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -322,6 +322,17 @@ For Cortex-A78 AE, the following errata build flags are defined : Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is still open. +For Cortex-X1 CPU, the following errata build flags are defined: + +- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 + CPU. This needs to be enabled only for revision <= r1p0 of the CPU. + +- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1 + CPU. This needs to be enabled only for revision <= r1p0 of the CPU. + +- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1 + CPU. This needs to be enabled only for revision <= r1p0 of the CPU. + For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 diff --git a/include/lib/cpus/aarch64/cortex_x1.h b/include/lib/cpus/aarch64/cortex_x1.h index 7ea7fddec..83be10d8e 100644 --- a/include/lib/cpus/aarch64/cortex_x1.h +++ b/include/lib/cpus/aarch64/cortex_x1.h @@ -15,6 +15,11 @@ ******************************************************************************/ #define CORTEX_X1_CPUECTLR_EL1 S3_0_C15_C1_4 +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_X1_ACTLR2_EL1 S3_0_C15_C1_1 + /******************************************************************************* * CPU Power Control register specific definitions ******************************************************************************/ diff --git a/lib/cpus/aarch64/cortex_x1.S b/lib/cpus/aarch64/cortex_x1.S index 3ec0f2d8f..c8bc190ea 100644 --- a/lib/cpus/aarch64/cortex_x1.S +++ b/lib/cpus/aarch64/cortex_x1.S @@ -18,8 +18,116 @@ #error "Cortex-X1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +/* -------------------------------------------------- + * Errata Workaround for X1 Erratum 1821534. + * This applies to revision r0p0 and r1p0 of X1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_x1_1821534_wa + /* Compare x0 against revision r1p0 */ + mov x17, x30 + bl check_errata_1821534 + cbz x0, 1f + mrs x1, CORTEX_X1_ACTLR2_EL1 + orr x1, x1, BIT(2) + msr CORTEX_X1_ACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_x1_1821534_wa + +func check_errata_1821534 + /* Applies to r0p0 and r1p0 */ + mov x1, #0x10 + b cpu_rev_var_ls +endfunc check_errata_1821534 + +/* -------------------------------------------------- + * Errata Workaround for X1 Erratum 1688305. + * This applies to revision r0p0 and r1p0 of X1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_x1_1688305_wa + /* Compare x0 against revision r1p0 */ + mov x17, x30 + bl check_errata_1688305 + cbz x0, 1f + mrs x0, CORTEX_X1_ACTLR2_EL1 + orr x0, x0, BIT(1) + msr CORTEX_X1_ACTLR2_EL1, x0 + isb + +1: + ret x17 +endfunc errata_x1_1688305_wa + +func check_errata_1688305 + /* Applies to r0p0 and r1p0 */ + mov x1, #0x10 + b cpu_rev_var_ls +endfunc check_errata_1688305 + +/* -------------------------------------------------- + * Errata Workaround for X1 Erratum 1827429. + * This applies to revision r0p0 and r1p0 of X1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_x1_1827429_wa + /* Compare x0 against revision r1p0 */ + mov x17, x30 + bl check_errata_1827429 + cbz x0, 1f + mrs x0, CORTEX_X1_CPUECTLR_EL1 + orr x0, x0, BIT(53) + msr CORTEX_X1_CPUECTLR_EL1, x0 + isb + +1: + ret x17 +endfunc errata_x1_1827429_wa + +func check_errata_1827429 + /* Applies to r0p0 and r1p0 */ + mov x1, #0x10 + b cpu_rev_var_ls +endfunc check_errata_1827429 + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-X1. + * Shall clobber: x0-x19 + * ------------------------------------------------- + */ func cortex_x1_reset_func - ret + mov x19, x30 + bl cpu_get_rev_var + mov x18, x0 + +#if ERRATA_X1_1821534 + mov x0, x18 + bl errata_x1_1821534_wa +#endif + +#if ERRATA_X1_1688305 + mov x0, x18 + bl errata_x1_1688305_wa +#endif + +#if ERRATA_X1_1827429 + mov x0, x18 + bl errata_x1_1827429_wa +#endif + + isb + ret x19 endfunc cortex_x1_reset_func /* --------------------------------------------- @@ -43,6 +151,20 @@ endfunc cortex_x1_core_pwr_dwn * Errata printing function for Cortex X1. Must follow AAPCS. */ func cortex_x1_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_X1_1821534, cortex_x1, 1821534 + report_errata ERRATA_X1_1688305, cortex_x1, 1688305 + report_errata ERRATA_X1_1827429, cortex_x1, 1827429 + + ldp x8, x30, [sp], #16 ret endfunc cortex_x1_errata_report #endif diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 2cbe13c45..eb17dfd36 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -357,6 +357,18 @@ ERRATA_A78_AE_2376748 ?=0 # to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open. ERRATA_A78_AE_2395408 ?=0 +# Flag to apply erratum 1821534 workaround during reset. This erratum applies +# to revisions r0p0 - r1p0 of the X1 cpu and fixed in r1p1. +ERRATA_X1_1821534 ?=0 + +# Flag to apply erratum 1688305 workaround during reset. This erratum applies +# to revisions r0p0 - r1p0 of the X1 cpu and fixed in r1p1. +ERRATA_X1_1688305 ?=0 + +# Flag to apply erratum 1827429 workaround during reset. This erratum applies +# to revisions r0p0 - r1p0 of the X1 cpu and fixed in r1p1. +ERRATA_X1_1827429 ?=0 + # Flag to apply T32 CLREX workaround during reset. This erratum applies # only to r0p0 and r1p0 of the Neoverse N1 cpu. ERRATA_N1_1043202 ?=0 @@ -878,6 +890,18 @@ $(eval $(call add_define,ERRATA_A78_AE_2376748)) $(eval $(call assert_boolean,ERRATA_A78_AE_2395408)) $(eval $(call add_define,ERRATA_A78_AE_2395408)) +# Process ERRATA_X1_1821534 flag +$(eval $(call assert_boolean,ERRATA_X1_1821534)) +$(eval $(call add_define,ERRATA_X1_1821534)) + +# Process ERRATA_X1_1688305 flag +$(eval $(call assert_boolean,ERRATA_X1_1688305)) +$(eval $(call add_define,ERRATA_X1_1688305)) + +# Process ERRATA_X1_1827429 flag +$(eval $(call assert_boolean,ERRATA_X1_1827429)) +$(eval $(call add_define,ERRATA_X1_1827429)) + # Process ERRATA_N1_1043202 flag $(eval $(call assert_boolean,ERRATA_N1_1043202)) $(eval $(call add_define,ERRATA_N1_1043202))