juno: Fix AArch32 build
Commit 6de8b24f52
broke Juno AArch32
build.
Change-Id: Ied70d9becb86e53ccb46a2e3245e2a551d1bf701
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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@ -81,9 +81,9 @@ func JUNO_HANDLER(0)
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* Cortex-A57 specific settings
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* --------------------------------------------------------------------
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*/
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mov r0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
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(L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
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stcopr r0, L2CTLR
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mov r0, #((CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
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(CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT))
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stcopr r0, CORTEX_A57_L2CTLR
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1:
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isb
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bx lr
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@ -118,8 +118,8 @@ A57:
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* Cortex-A57 specific settings
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* --------------------------------------------------------------------
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*/
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mov r0, #(L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT)
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stcopr r0, L2CTLR
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mov r0, #(CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT)
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stcopr r0, CORTEX_A57_L2CTLR
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isb
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bx lr
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endfunc JUNO_HANDLER(1)
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@ -152,9 +152,9 @@ A72:
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* Cortex-A72 specific settings
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* --------------------------------------------------------------------
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*/
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mov r0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
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(L2_TAG_RAM_LATENCY_2_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
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stcopr r0, L2CTLR
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mov r0, #((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
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(CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES << CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT))
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stcopr r0, CORTEX_A72_L2CTLR
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isb
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bx lr
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endfunc JUNO_HANDLER(2)
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