rcar_gen3: drivers: pwrc: Switch to common delay implementation
Replace the ad-hoc implementation of delay in PWRC driver with common R-Car delay code. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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@ -17,6 +17,7 @@
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#include "iic_dvfs.h"
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#include "rcar_def.h"
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#include "rcar_private.h"
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#include "micro_delay.h"
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#include "pwrc.h"
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/*
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@ -122,7 +123,6 @@ RCAR_INSTANTIATE_LOCK
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#define RST_BASE (0xE6160000U)
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#define RST_MODEMR (RST_BASE + 0x0060U)
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#define RST_MODEMR_BIT0 (0x00000001U)
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#define RCAR_CONV_MICROSEC (1000000U)
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#if PMIC_ROHM_BD9571
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#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
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@ -143,23 +143,6 @@ IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END);
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IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START);
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#endif
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#if RCAR_SYSTEM_SUSPEND
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static void __attribute__ ((section (".system_ram")))
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rcar_pwrc_micro_delay(uint64_t micro_sec)
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{
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uint64_t freq, base, val;
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uint64_t wait_time = 0;
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freq = read_cntfrq_el0();
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base = read_cntpct_el0();
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while (micro_sec > wait_time) {
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val = read_cntpct_el0() - base;
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wait_time = val * RCAR_CONV_MICROSEC / freq;
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}
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}
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#endif
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uint32_t rcar_pwrc_status(uint64_t mpidr)
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{
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uint32_t ret = 0;
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@ -414,7 +397,7 @@ self_refresh:
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mmio_write_32(DBSC4_REG_DBACEN, 0);
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if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
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rcar_pwrc_micro_delay(100);
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rcar_micro_delay(100);
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else if (product == RCAR_PRODUCT_H3) {
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mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
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DBCAM_FLUSH(0);
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@ -465,7 +448,7 @@ self_refresh:
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/* Set the auto-refresh enable register */
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mmio_write_32(DBSC4_REG_DBRFEN, 0U);
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rcar_pwrc_micro_delay(1U);
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rcar_micro_delay(1U);
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if (product == RCAR_PRODUCT_M3)
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return;
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@ -378,6 +378,7 @@ BL31_SOURCES += ${RCAR_GIC_SOURCES} \
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plat/renesas/rcar/plat_pm.c \
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drivers/renesas/rcar/console/rcar_console.S \
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drivers/renesas/rcar/console/rcar_printf.c \
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drivers/renesas/rcar/delay/micro_delay.c \
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drivers/renesas/rcar/pwrc/call_sram.S \
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drivers/renesas/rcar/pwrc/pwrc.c \
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drivers/renesas/rcar/common.c \
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