feat(plat/mediatek/apu): add mt8192 APU SiP call support
Add APU SiP call support for start/stop mcu. Signed-off-by: Flora Fu <flora.fu@mediatek.com> Change-Id: Ibf93d8ccf22c414de3093cee9e13f7668588f69e Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@mediatek.com>
This commit is contained in:
Flora Fu
parent
2671f31872
commit
ca4c0c2e78
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@ -35,6 +35,10 @@
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#define MTK_SIP_VCORE_CONTROL_ARCH32 0x82000506
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#define MTK_SIP_VCORE_CONTROL_ARCH64 0xC2000506
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/* APUSYS SMC call */
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#define MTK_SIP_APUSYS_CONTROL_AARCH32 0x8200051E
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#define MTK_SIP_APUSYS_CONTROL_AARCH64 0xC200051E
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/* Mediatek SiP Calls error code */
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enum {
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MTK_SIP_E_SUCCESS = 0,
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@ -0,0 +1,68 @@
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/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <drivers/console.h>
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#include <lib/mmio.h>
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#include <mtk_apusys.h>
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#include <plat/common/platform.h>
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uint64_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
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uint32_t *ret1)
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{
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uint32_t request_ops;
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request_ops = (uint32_t)x1;
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INFO("[APUSYS] ops=0x%x\n", request_ops);
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switch (request_ops) {
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case MTK_SIP_APU_START_MCU:
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/* setup addr[33:32] in reviser */
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mmio_write_32(REVISER_SECUREFW_CTXT, 0U);
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mmio_write_32(REVISER_USDRFW_CTXT, 0U);
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/* setup secure sideband */
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mmio_write_32(AO_SEC_FW,
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(SEC_FW_NON_SECURE << SEC_FW_SHIFT_NS) |
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(0U << SEC_FW_DOMAIN_SHIFT));
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/* setup boot address */
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mmio_write_32(AO_MD32_BOOT_CTRL, 0U);
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/* setup pre-define region */
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mmio_write_32(AO_MD32_PRE_DEFINE,
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(PRE_DEFINE_CACHE_TCM << PRE_DEFINE_SHIFT_0G) |
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(PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_1G) |
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(PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_2G) |
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(PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_3G));
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/* release runstall */
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mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_RUN);
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INFO("[APUSYS] reviser_ctxt=%x,%x\n",
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mmio_read_32(REVISER_SECUREFW_CTXT),
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mmio_read_32(REVISER_USDRFW_CTXT));
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INFO("[APUSYS]fw=0x%08x,boot=0x%08x,def=0x%08x,sys=0x%08x\n",
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mmio_read_32(AO_SEC_FW),
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mmio_read_32(AO_MD32_BOOT_CTRL),
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mmio_read_32(AO_MD32_PRE_DEFINE),
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mmio_read_32(AO_MD32_SYS_CTRL));
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break;
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case MTK_SIP_APU_STOP_MCU:
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/* hold runstall */
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mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_STALL);
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INFO("[APUSYS] md32_boot_ctrl=0x%08x,runstall=0x%08x\n",
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mmio_read_32(AO_MD32_BOOT_CTRL),
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mmio_read_32(AO_MD32_SYS_CTRL));
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break;
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default:
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ERROR("%s, unknown request_ops = %x\n", __func__, request_ops);
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break;
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}
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return 0UL;
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}
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@ -0,0 +1,42 @@
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/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __MTK_APUSYS_H__
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#define __MTK_APUSYS_H__
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#include <stdint.h>
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/* setup the SMC command ops */
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#define MTK_SIP_APU_START_MCU 0x00U
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#define MTK_SIP_APU_STOP_MCU 0x01U
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/* AO Register */
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#define AO_MD32_PRE_DEFINE (APUSYS_APU_S_S_4_BASE + 0x00)
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#define AO_MD32_BOOT_CTRL (APUSYS_APU_S_S_4_BASE + 0x04)
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#define AO_MD32_SYS_CTRL (APUSYS_APU_S_S_4_BASE + 0x08)
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#define AO_SEC_FW (APUSYS_APU_S_S_4_BASE + 0x10)
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#define PRE_DEFINE_CACHE_TCM 0x3U
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#define PRE_DEFINE_CACHE 0x2U
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#define PRE_DEFINE_SHIFT_0G 0U
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#define PRE_DEFINE_SHIFT_1G 2U
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#define PRE_DEFINE_SHIFT_2G 4U
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#define PRE_DEFINE_SHIFT_3G 6U
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#define SEC_FW_NON_SECURE 1U
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#define SEC_FW_SHIFT_NS 4U
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#define SEC_FW_DOMAIN_SHIFT 0U
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#define SYS_CTRL_RUN 0U
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#define SYS_CTRL_STALL 1U
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/* Reviser Register */
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#define REVISER_SECUREFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x300)
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#define REVISER_USDRFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x304)
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uint64_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
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uint32_t *ret1);
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#endif /* __MTK_APUSYS_H__ */
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@ -6,6 +6,7 @@
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <mtk_apusys.h>
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#include <mtk_sip_svc.h>
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#include <mt_spm_vcorefs.h>
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#include "plat_sip_calls.h"
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@ -20,6 +21,7 @@ uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
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u_register_t flags)
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{
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uint64_t ret;
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uint32_t rnd_val0 = 0U;
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switch (smc_fid) {
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case MTK_SIP_VCORE_CONTROL_ARCH32:
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@ -27,6 +29,11 @@ uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
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ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4);
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SMC_RET2(handle, ret, x4);
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break;
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case MTK_SIP_APUSYS_CONTROL_AARCH32:
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case MTK_SIP_APUSYS_CONTROL_AARCH64:
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ret = apusys_kernel_ctrl(x1, x2, x3, x4, &rnd_val0);
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SMC_RET2(handle, ret, rnd_val0);
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break;
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default:
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ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
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break;
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@ -16,6 +16,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
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-I${MTK_PLAT}/common/lpm/ \
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-I${MTK_PLAT_SOC}/include/ \
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-I${MTK_PLAT_SOC}/drivers/ \
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-I${MTK_PLAT_SOC}/drivers/apusys/ \
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-I${MTK_PLAT_SOC}/drivers/dcm \
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-I${MTK_PLAT_SOC}/drivers/devapc \
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-I${MTK_PLAT_SOC}/drivers/emi_mpu/ \
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@ -62,6 +63,7 @@ BL31_SOURCES += common/desc_image_load.c \
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${MTK_PLAT_SOC}/plat_pm.c \
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${MTK_PLAT_SOC}/plat_topology.c \
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${MTK_PLAT_SOC}/plat_sip_calls.c \
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${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys.c \
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${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \
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${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \
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${MTK_PLAT_SOC}/drivers/devapc/devapc.c \
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