RAS: Allow individual interrupt registration

EHF currently allows for registering interrupt handlers for a defined
priority ranges. This is primarily targeted at various EL3 dispatchers
to own ranges of secure interrupt priorities in order to delegate
execution to lower ELs.

The RAS support added by earlier patches necessitates registering
handlers based on interrupt number so that error handling agents shall
receive and handle specific Error Recovery or Fault Handling interrupts
at EL3.

This patch introduces a macro, RAS_INTERRUPTS() to declare an array of
interrupt numbers and handlers. Error handling agents can use this macro
to register handlers for individual RAS interrupts. The array is
expected to be sorted in the increasing order of interrupt numbers.

As part of RAS initialisation, the list of all RAS interrupts are sorted
based on their ID so that, given an interrupt, its handler can be looked
up with a simple binary search.

For an error handling agent that wants to handle a RAS interrupt,
platform must:

  - Define PLAT_RAS_PRI to be the priority of all RAS exceptions.

  - Enumerate interrupts to have the GIC driver program individual EL3
    interrupts to the required priority range. This is required by EHF
    even before this patch.

Documentation to follow.

Change-Id: I9471e4887ff541f8a7a63309e9cd8f771f76aeda
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
This commit is contained in:
Jeenu Viswambharan 2017-12-12 10:34:58 +00:00
parent 362599eca4
commit ca6d918582
3 changed files with 121 additions and 0 deletions

View File

@ -18,4 +18,7 @@
/* External Abort synchronized by ESB instruction */
#define ERROR_EA_ESB 2
/* RAS event signalled as peripheral interrupt */
#define ERROR_INTERRUPT 3
#endif /* __EA_HANDLE_H__ */

View File

@ -54,6 +54,20 @@
_ERR_RECORD_COMMON(_probe, _handler, _aux) \
}
/*
* Macro to be used to name and declare an array of RAS interrupts along with
* their handlers.
*
* This macro must be used in the same file as the array of interrupts are
* declared. Only then would ARRAY_SIZE() yield a meaningful value. Also, the
* array is expected to be sorted in the increasing order of interrupt number.
*/
#define REGISTER_RAS_INTERRUPTS(_array) \
const struct ras_interrupt_mapping ras_interrupt_mapping = { \
.intrs = _array, \
.num_intrs = ARRAY_SIZE(_array), \
}
#ifndef __ASSEMBLY__
#include <assert.h>
@ -61,6 +75,13 @@
struct err_record_info;
struct ras_interrupt {
/* Interrupt number, and the associated error record info */
unsigned int intr_number;
struct err_record_info *err_record;
void *cookie;
};
/* Function to probe a error record group for error */
typedef int (*err_record_probe_t)(const struct err_record_info *info,
int *probe_data);
@ -83,6 +104,9 @@ struct err_handler_data {
* synchronized by ESB, the value of DISR.
*/
uint32_t syndrome;
/* For errors signalled via. interrupt, the raw interrupt ID; otherwise, 0. */
unsigned int interrupt;
};
/* Function to handle error from an error record group */
@ -136,7 +160,13 @@ struct err_record_mapping {
size_t num_err_records;
};
struct ras_interrupt_mapping {
struct ras_interrupt *intrs;
size_t num_intrs;
};
extern const struct err_record_mapping err_record_mapping;
extern const struct ras_interrupt_mapping ras_interrupt_mapping;
/*
@ -163,6 +193,7 @@ static inline int ras_err_ser_probe_sysreg(const struct err_record_info *info,
int ras_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
void *handle, uint64_t flags);
void ras_init(void);
#endif /* __ASSEMBLY__ */
#endif /* __RAS_COMMON__ */

View File

@ -12,6 +12,10 @@
#include <ras.h>
#include <ras_arch.h>
#ifndef PLAT_RAS_PRI
# error Platform must define RAS priority value
#endif
/* Handler that receives External Aborts on RAS-capable systems */
int ras_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
void *handle, uint64_t flags)
@ -23,6 +27,7 @@ int ras_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
const struct err_handler_data err_data = {
.version = ERR_HANDLER_VERSION,
.ea_reason = ea_reason,
.interrupt = 0,
.syndrome = syndrome,
.flags = flags,
.cookie = cookie,
@ -49,3 +54,85 @@ int ras_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
return (n_handled != 0);
}
#if ENABLE_ASSERTIONS
static void assert_interrupts_sorted(void)
{
unsigned int i, last;
struct ras_interrupt *start = ras_interrupt_mapping.intrs;
if (ras_interrupt_mapping.num_intrs == 0)
return;
last = start[0].intr_number;
for (i = 1; i < ras_interrupt_mapping.num_intrs; i++) {
assert(start[i].intr_number > last);
last = start[i].intr_number;
}
}
#endif
/*
* Given an RAS interrupt number, locate the registered handler and call it. If
* no handler was found for the interrupt number, this function panics.
*/
static int ras_interrupt_handler(uint32_t intr_raw, uint32_t flags,
void *handle, void *cookie)
{
struct ras_interrupt *ras_inrs = ras_interrupt_mapping.intrs;
struct ras_interrupt *selected = NULL;
int start, end, mid, probe_data, ret __unused;
const struct err_handler_data err_data = {
.version = ERR_HANDLER_VERSION,
.interrupt = intr_raw,
.flags = flags,
.cookie = cookie,
.handle = handle
};
assert(ras_interrupt_mapping.num_intrs > 0);
start = 0;
end = ras_interrupt_mapping.num_intrs;
while (start <= end) {
mid = ((end + start) / 2);
if (intr_raw == ras_inrs[mid].intr_number) {
selected = &ras_inrs[mid];
break;
} else if (intr_raw < ras_inrs[mid].intr_number) {
/* Move left */
end = mid - 1;
} else {
/* Move right */
start = mid + 1;
}
}
if (selected == NULL) {
ERROR("RAS interrupt %u has no handler!\n", intr_raw);
panic();
}
ret = selected->err_record->probe(selected->err_record, &probe_data);
assert(ret != 0);
/* Call error handler for the record group */
assert(selected->err_record->handler != NULL);
selected->err_record->handler(selected->err_record, probe_data,
&err_data);
return 0;
}
void ras_init(void)
{
#if ENABLE_ASSERTIONS
/* Check RAS interrupts are sorted */
assert_interrupts_sorted();
#endif
/* Register RAS priority handler */
ehf_register_priority_handler(PLAT_RAS_PRI, ras_interrupt_handler);
}