Merge pull request #1683 from Yann-lms/stm32mp1_multi_console
Add multi console support for STM32MP1
This commit is contained in:
Antonio Niño Díaz
GitHub
commit
cabe0a3180
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@ -4,30 +4,27 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <assert_macros.S>
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#define USE_FINISH_CONSOLE_REG_2
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#include <console_macros.S>
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#include <stm32_console.h>
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#include <stm32_uart_regs.h>
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#define USART_TIMEOUT 0x1000
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#define USART_CR1 0x00
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#define USART_CR1_UE 0x00000001
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#define USART_CR1_TE 0x00000008
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#define USART_CR1_FIFOEN 0x20000000
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/*
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* "core" functions are low-level implementations that don't require
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* writeable memory and are thus safe to call in BL1 crash context.
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*/
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.globl console_stm32_core_init
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.globl console_stm32_core_putc
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.globl console_stm32_core_getc
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.globl console_stm32_core_flush
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#define USART_CR2 0x04
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#define USART_CR2_STOP 0x00003000
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.globl console_stm32_putc
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.globl console_stm32_flush
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#define USART_BRR 0x0C
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#define USART_ISR 0x1C
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#define USART_ISR_TC 0x00000040
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#define USART_ISR_TXE 0x00000080
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#define USART_ISR_TEACK 0x00200000
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#define USART_TDR 0x28
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.globl console_core_init
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.globl console_core_putc
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.globl console_core_getc
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.globl console_core_flush
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/* -----------------------------------------------------------------
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* int console_core_init(uintptr_t base_addr,
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@ -45,7 +42,7 @@
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* Clobber list : r1, r2, r3
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* -----------------------------------------------------------------
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*/
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func console_core_init
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func console_stm32_core_init
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/* Check the input base address */
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cmp r0, #0
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beq core_init_fail
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@ -88,7 +85,43 @@ teack_loop:
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core_init_fail:
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mov r0, #0
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bx lr
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endfunc console_core_init
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endfunc console_stm32_core_init
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.globl console_stm32_register
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/* -------------------------------------------------------
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* int console_stm32_register(uintptr_t baseaddr,
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* uint32_t clock, uint32_t baud,
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* struct console_stm32 *console);
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* Function to initialize and register a new STM32
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* console. Storage passed in for the console struct
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* *must* be persistent (i.e. not from the stack).
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* In: r0 - UART register base address
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* r1 - UART clock in Hz
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* r2 - Baud rate
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* r3 - pointer to empty console_stm32 struct
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* Out: return 1 on success, 0 on error
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* Clobber list : r0, r1, r2
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* -------------------------------------------------------
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*/
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func console_stm32_register
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push {r4, lr}
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mov r4, r3
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cmp r4, #0
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beq register_fail
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str r0, [r4, #CONSOLE_T_STM32_BASE]
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bl console_stm32_core_init
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cmp r0, #0
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beq register_fail
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mov r0, r4
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pop {r4, lr}
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finish_console_register stm32 putc=1, getc=0, flush=1
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register_fail:
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pop {r4, pc}
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endfunc console_stm32_register
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/* ---------------------------------------------------------------
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* int console_core_putc(int c, uintptr_t base_addr)
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@ -102,7 +135,7 @@ endfunc console_core_init
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* Clobber list : r2
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* ---------------------------------------------------------------
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*/
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func console_core_putc
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func console_stm32_core_putc
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/* Check the input parameter */
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cmp r1, #0
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beq putc_error
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@ -138,7 +171,26 @@ tc_loop_2:
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putc_error:
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mov r0, #-1
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bx lr
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endfunc console_core_putc
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endfunc console_stm32_core_putc
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/* ------------------------------------------------------------
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* int console_stm32_putc(int c, struct console_stm32 *console)
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* Function to output a character over the console. It
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* returns the character printed on success or -1 on error.
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* In: r0 - character to be printed
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* r1 - pointer to console_t structure
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* Out : return -1 on error else return character.
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* Clobber list: r2
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* ------------------------------------------------------------
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*/
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func console_stm32_putc
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#if ENABLE_ASSERTIONS
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cmp r1, #0
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ASM_ASSERT(ne)
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#endif /* ENABLE_ASSERTIONS */
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ldr r1, [r1, #CONSOLE_T_STM32_BASE]
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b console_stm32_core_putc
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endfunc console_stm32_putc
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/* -----------------------------------------------------------
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* int console_core_getc(uintptr_t base_addr)
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@ -151,11 +203,11 @@ endfunc console_core_putc
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* Clobber list : r0, r1
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* -----------------------------------------------------------
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*/
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func console_core_getc
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func console_stm32_core_getc
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/* Not supported */
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mov r0, #-1
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bx lr
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endfunc console_core_getc
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endfunc console_stm32_core_getc
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/* ---------------------------------------------------------------
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* int console_core_flush(uintptr_t base_addr)
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@ -168,7 +220,7 @@ endfunc console_core_getc
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* Clobber list : r0, r1
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* ---------------------------------------------------------------
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*/
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func console_core_flush
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func console_stm32_core_flush
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cmp r0, #0
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beq flush_error
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/* Check Transmit Data Register Empty */
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@ -181,4 +233,22 @@ txe_loop_3:
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flush_error:
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mov r0, #-1
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bx lr
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endfunc console_core_flush
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endfunc console_stm32_core_flush
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/* ------------------------------------------------------
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* int console_stm32_flush(struct console_stm32 *console)
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* Function to force a write of all buffered
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* data that hasn't been output.
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* In : r0 - pointer to console_t structure
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* Out : return -1 on error else return 0.
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* Clobber list: r0, r1
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* ------------------------------------------------------
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*/
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func console_stm32_flush
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#if ENABLE_ASSERTIONS
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cmp r0, #0
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ASM_ASSERT(ne)
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#endif /* ENABLE_ASSERTIONS */
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ldr r0, [r0, #CONSOLE_T_STM32_BASE]
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b console_stm32_core_flush
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endfunc console_stm32_flush
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@ -0,0 +1,34 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32_CONSOLE_H
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#define STM32_CONSOLE_H
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#include <console.h>
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#define CONSOLE_T_STM32_BASE CONSOLE_T_DRVDATA
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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struct console_stm32 {
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console_t console;
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uintptr_t base;
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};
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/*
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* Initialize a new STM32 console instance and register it with the console
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* framework. The |console| pointer must point to storage that will be valid
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* for the lifetime of the console, such as a global or static local variable.
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* Its contents will be reinitialized from scratch.
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*/
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int console_stm32_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
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struct console_stm32 *console);
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#endif /*__ASSEMBLY__*/
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#endif /* STM32_CONSOLE_H */
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@ -0,0 +1,199 @@
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32_UART_REGS_H
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#define STM32_UART_REGS_H
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#include <utils_def.h>
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#define USART_CR1 U(0x00)
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#define USART_CR2 U(0x04)
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#define USART_CR3 U(0x08)
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#define USART_BRR U(0x0C)
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#define USART_GTPR U(0x10)
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#define USART_RTOR U(0x14)
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#define USART_RQR U(0x18)
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#define USART_ISR U(0x1C)
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#define USART_ICR U(0x20)
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#define USART_RDR U(0x24)
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#define USART_TDR U(0x28)
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#define USART_PRESC U(0x2C)
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/* USART_CR1 register fields */
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#define USART_CR1_UE BIT(0)
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#define USART_CR1_UESM BIT(1)
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#define USART_CR1_RE BIT(2)
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#define USART_CR1_TE BIT(3)
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#define USART_CR1_IDLEIE BIT(4)
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#define USART_CR1_RXNEIE BIT(5)
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#define USART_CR1_TCIE BIT(6)
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#define USART_CR1_TXEIE BIT(7)
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#define USART_CR1_PEIE BIT(8)
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#define USART_CR1_PS BIT(9)
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#define USART_CR1_PCE BIT(10)
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#define USART_CR1_WAKE BIT(11)
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#define USART_CR1_M (BIT(28) | BIT(12))
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#define USART_CR1_M0 BIT(12)
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#define USART_CR1_MME BIT(13)
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#define USART_CR1_CMIE BIT(14)
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#define USART_CR1_OVER8 BIT(15)
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#define USART_CR1_DEDT GENMASK(20, 16)
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#define USART_CR1_DEDT_0 BIT(16)
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#define USART_CR1_DEDT_1 BIT(17)
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#define USART_CR1_DEDT_2 BIT(18)
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#define USART_CR1_DEDT_3 BIT(19)
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#define USART_CR1_DEDT_4 BIT(20)
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#define USART_CR1_DEAT GENMASK(25, 21)
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#define USART_CR1_DEAT_0 BIT(21)
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#define USART_CR1_DEAT_1 BIT(22)
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#define USART_CR1_DEAT_2 BIT(23)
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#define USART_CR1_DEAT_3 BIT(24)
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#define USART_CR1_DEAT_4 BIT(25)
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#define USART_CR1_RTOIE BIT(26)
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#define USART_CR1_EOBIE BIT(27)
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#define USART_CR1_M1 BIT(28)
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#define USART_CR1_FIFOEN BIT(29)
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#define USART_CR1_TXFEIE BIT(30)
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#define USART_CR1_RXFFIE BIT(31)
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/* USART_CR2 register fields */
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#define USART_CR2_SLVEN BIT(0)
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#define USART_CR2_DIS_NSS BIT(3)
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#define USART_CR2_ADDM7 BIT(4)
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#define USART_CR2_LBDL BIT(5)
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#define USART_CR2_LBDIE BIT(6)
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#define USART_CR2_LBCL BIT(8)
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#define USART_CR2_CPHA BIT(9)
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#define USART_CR2_CPOL BIT(10)
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#define USART_CR2_CLKEN BIT(11)
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#define USART_CR2_STOP GENMASK(13, 12)
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#define USART_CR2_STOP_0 BIT(12)
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#define USART_CR2_STOP_1 BIT(13)
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#define USART_CR2_LINEN BIT(14)
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#define USART_CR2_SWAP BIT(15)
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#define USART_CR2_RXINV BIT(16)
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#define USART_CR2_TXINV BIT(17)
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#define USART_CR2_DATAINV BIT(18)
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#define USART_CR2_MSBFIRST BIT(19)
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#define USART_CR2_ABREN BIT(20)
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#define USART_CR2_ABRMODE GENMASK(22, 21)
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#define USART_CR2_ABRMODE_0 BIT(21)
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#define USART_CR2_ABRMODE_1 BIT(22)
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#define USART_CR2_RTOEN BIT(23)
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#define USART_CR2_ADD GENMASK(31, 24)
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/* USART_CR3 register fields */
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#define USART_CR3_EIE BIT(0)
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#define USART_CR3_IREN BIT(1)
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#define USART_CR3_IRLP BIT(2)
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#define USART_CR3_HDSEL BIT(3)
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#define USART_CR3_NACK BIT(4)
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#define USART_CR3_SCEN BIT(5)
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#define USART_CR3_DMAR BIT(6)
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#define USART_CR3_DMAT BIT(7)
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#define USART_CR3_RTSE BIT(8)
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#define USART_CR3_CTSE BIT(9)
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#define USART_CR3_CTSIE BIT(10)
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#define USART_CR3_ONEBIT BIT(11)
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#define USART_CR3_OVRDIS BIT(12)
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#define USART_CR3_DDRE BIT(13)
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#define USART_CR3_DEM BIT(14)
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#define USART_CR3_DEP BIT(15)
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#define USART_CR3_SCARCNT GENMASK(19, 17)
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#define USART_CR3_SCARCNT_0 BIT(17)
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#define USART_CR3_SCARCNT_1 BIT(18)
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#define USART_CR3_SCARCNT_2 BIT(19)
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#define USART_CR3_WUS GENMASK(21, 20)
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#define USART_CR3_WUS_0 BIT(20)
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#define USART_CR3_WUS_1 BIT(21)
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#define USART_CR3_WUFIE BIT(22)
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#define USART_CR3_TXFTIE BIT(23)
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#define USART_CR3_TCBGTIE BIT(24)
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#define USART_CR3_RXFTCFG GENMASK(27, 25)
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#define USART_CR3_RXFTCFG_0 BIT(25)
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#define USART_CR3_RXFTCFG_1 BIT(26)
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#define USART_CR3_RXFTCFG_2 BIT(27)
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#define USART_CR3_RXFTIE BIT(28)
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#define USART_CR3_TXFTCFG GENMASK(31, 29)
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#define USART_CR3_TXFTCFG_0 BIT(29)
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#define USART_CR3_TXFTCFG_1 BIT(30)
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#define USART_CR3_TXFTCFG_2 BIT(31)
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/* USART_BRR register fields */
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#define USART_BRR_DIV_FRACTION GENMASK(3, 0)
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#define USART_BRR_DIV_MANTISSA GENMASK(15, 4)
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/* USART_GTPR register fields */
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#define USART_GTPR_PSC GENMASK(7, 0)
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#define USART_GTPR_GT GENMASK(15, 8)
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/* USART_RTOR register fields */
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#define USART_RTOR_RTO GENMASK(23, 0)
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#define USART_RTOR_BLEN GENMASK(31, 24)
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/* USART_RQR register fields */
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#define USART_RQR_ABRRQ BIT(0)
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#define USART_RQR_SBKRQ BIT(1)
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#define USART_RQR_MMRQ BIT(2)
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#define USART_RQR_RXFRQ BIT(3)
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#define USART_RQR_TXFRQ BIT(4)
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/* USART_ISR register fields */
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#define USART_ISR_PE BIT(0)
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#define USART_ISR_FE BIT(1)
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#define USART_ISR_NE BIT(2)
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#define USART_ISR_ORE BIT(3)
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#define USART_ISR_IDLE BIT(4)
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#define USART_ISR_RXNE BIT(5)
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#define USART_ISR_TC BIT(6)
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#define USART_ISR_TXE BIT(7)
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#define USART_ISR_LBDF BIT(8)
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#define USART_ISR_CTSIF BIT(9)
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#define USART_ISR_CTS BIT(10)
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#define USART_ISR_RTOF BIT(11)
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#define USART_ISR_EOBF BIT(12)
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#define USART_ISR_UDR BIT(13)
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#define USART_ISR_ABRE BIT(14)
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#define USART_ISR_ABRF BIT(15)
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#define USART_ISR_BUSY BIT(16)
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#define USART_ISR_CMF BIT(17)
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#define USART_ISR_SBKF BIT(18)
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#define USART_ISR_RWU BIT(19)
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#define USART_ISR_WUF BIT(20)
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#define USART_ISR_TEACK BIT(21)
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#define USART_ISR_REACK BIT(22)
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#define USART_ISR_TXFE BIT(23)
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#define USART_ISR_RXFF BIT(24)
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#define USART_ISR_TCBGT BIT(25)
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#define USART_ISR_RXFT BIT(26)
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#define USART_ISR_TXFT BIT(27)
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/* USART_ICR register fields */
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#define USART_ICR_PECF BIT(0)
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#define USART_ICR_FECF BIT(1)
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#define USART_ICR_NCF BIT(2)
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#define USART_ICR_ORECF BIT(3)
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#define USART_ICR_IDLECF BIT(4)
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#define USART_ICR_TCCF BIT(6)
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#define USART_ICR_TCBGT BIT(7)
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#define USART_ICR_LBDCF BIT(8)
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#define USART_ICR_CTSCF BIT(9)
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#define USART_ICR_RTOCF BIT(11)
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#define USART_ICR_EOBCF BIT(12)
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#define USART_ICR_UDRCF BIT(13)
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#define USART_ICR_CMCF BIT(17)
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#define USART_ICR_WUCF BIT(20)
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/* USART_RDR register fields */
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#define USART_RDR_RDR GENMASK(8, 0)
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/* USART_TDR register fields */
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#define USART_TDR_TDR GENMASK(8, 0)
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/* USART_PRESC register fields */
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#define USART_PRESC_PRESCALER GENMASK(3, 0)
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|
||||
#endif /* STM32_UART_REGS_H */
|
||||
|
|
@ -30,11 +30,19 @@
|
|||
* position @h. For example
|
||||
* GENMASK_64(39, 21) gives us the 64bit vector 0x000000ffffe00000.
|
||||
*/
|
||||
#if defined(__LINKER__) || defined(__ASSEMBLY__)
|
||||
#define GENMASK_32(h, l) \
|
||||
(((0xFFFFFFFF) << (l)) & (0xFFFFFFFF >> (32 - 1 - (h))))
|
||||
|
||||
#define GENMASK_64(h, l) \
|
||||
((~0 << (l)) & (~0 >> (64 - 1 - (h))))
|
||||
#else
|
||||
#define GENMASK_32(h, l) \
|
||||
(((~UINT32_C(0)) << (l)) & (~UINT32_C(0) >> (32 - 1 - (h))))
|
||||
|
||||
#define GENMASK_64(h, l) \
|
||||
(((~UINT64_C(0)) << (l)) & (~UINT64_C(0) >> (64 - 1 - (h))))
|
||||
#endif
|
||||
|
||||
#ifdef AARCH32
|
||||
#define GENMASK GENMASK_32
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@
|
|||
#include <assert.h>
|
||||
#include <bl_common.h>
|
||||
#include <boot_api.h>
|
||||
#include <console.h>
|
||||
#include <debug.h>
|
||||
#include <delay_timer.h>
|
||||
#include <desc_image_load.h>
|
||||
|
|
@ -16,11 +15,12 @@
|
|||
#include <mmio.h>
|
||||
#include <platform.h>
|
||||
#include <platform_def.h>
|
||||
#include <stm32_console.h>
|
||||
#include <stm32mp1_clk.h>
|
||||
#include <stm32mp1_context.h>
|
||||
#include <stm32mp1_dt.h>
|
||||
#include <stm32mp1_pmic.h>
|
||||
#include <stm32mp1_private.h>
|
||||
#include <stm32mp1_context.h>
|
||||
#include <stm32mp1_pwr.h>
|
||||
#include <stm32mp1_ram.h>
|
||||
#include <stm32mp1_rcc.h>
|
||||
|
|
@ -28,6 +28,8 @@
|
|||
#include <string.h>
|
||||
#include <xlat_tables_v2.h>
|
||||
|
||||
static struct console_stm32 console;
|
||||
|
||||
void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
|
||||
u_register_t arg2, u_register_t arg3)
|
||||
{
|
||||
|
|
@ -137,8 +139,8 @@ void bl2_el3_plat_arch_setup(void)
|
|||
|
||||
clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_dev_info.clock);
|
||||
|
||||
if (console_init(dt_dev_info.base, clk_rate,
|
||||
STM32MP1_UART_BAUDRATE) == 0) {
|
||||
if (console_stm32_register(dt_dev_info.base, clk_rate,
|
||||
STM32MP1_UART_BAUDRATE, &console) == 0) {
|
||||
panic();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ ARM_CORTEX_A7 := yes
|
|||
ARM_WITH_NEON := yes
|
||||
BL2_AT_EL3 := 1
|
||||
USE_COHERENT_MEM := 0
|
||||
MULTI_CONSOLE_API := 1
|
||||
|
||||
STM32_TF_VERSION ?= 0
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,6 @@
|
|||
#include <arch_helpers.h>
|
||||
#include <assert.h>
|
||||
#include <bl_common.h>
|
||||
#include <console.h>
|
||||
#include <context.h>
|
||||
#include <context_mgmt.h>
|
||||
#include <debug.h>
|
||||
|
|
@ -17,6 +16,7 @@
|
|||
#include <platform.h>
|
||||
#include <platform_def.h>
|
||||
#include <platform_sp_min.h>
|
||||
#include <stm32_console.h>
|
||||
#include <stm32mp1_clk.h>
|
||||
#include <stm32mp1_dt.h>
|
||||
#include <stm32mp1_private.h>
|
||||
|
|
@ -30,6 +30,8 @@
|
|||
******************************************************************************/
|
||||
static entry_point_info_t bl33_image_ep_info;
|
||||
|
||||
static struct console_stm32 console;
|
||||
|
||||
/*******************************************************************************
|
||||
* Interrupt handler for FIQ (secure IRQ)
|
||||
******************************************************************************/
|
||||
|
|
@ -112,8 +114,9 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
|
|||
result = dt_get_stdout_uart_info(&dt_dev_info);
|
||||
|
||||
if ((result > 0) && dt_dev_info.status) {
|
||||
if (console_init(dt_dev_info.base, 0, STM32MP1_UART_BAUDRATE)
|
||||
== 0) {
|
||||
if (console_stm32_register(dt_dev_info.base, 0,
|
||||
STM32MP1_UART_BAUDRATE, &console) ==
|
||||
0) {
|
||||
panic();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -149,7 +149,7 @@ func plat_crash_console_init
|
|||
ldr r0, =STM32MP1_DEBUG_USART_BASE
|
||||
ldr r1, =STM32MP1_HSI_CLK
|
||||
ldr r2, =STM32MP1_UART_BAUDRATE
|
||||
b console_core_init
|
||||
b console_stm32_core_init
|
||||
endfunc plat_crash_console_init
|
||||
|
||||
/* ---------------------------------------------
|
||||
|
|
@ -160,7 +160,7 @@ endfunc plat_crash_console_init
|
|||
*/
|
||||
func plat_crash_console_flush
|
||||
ldr r1, =STM32MP1_DEBUG_USART_BASE
|
||||
b console_core_flush
|
||||
b console_stm32_core_flush
|
||||
endfunc plat_crash_console_flush
|
||||
|
||||
/* ---------------------------------------------
|
||||
|
|
@ -176,5 +176,5 @@ endfunc plat_crash_console_flush
|
|||
*/
|
||||
func plat_crash_console_putc
|
||||
ldr r1, =STM32MP1_DEBUG_USART_BASE
|
||||
b console_core_putc
|
||||
b console_stm32_core_putc
|
||||
endfunc plat_crash_console_putc
|
||||
|
|
|
|||
Loading…
Reference in New Issue