diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c index f5198f686..0edf6ba09 100644 --- a/plat/arm/board/fvp/fvp_common.c +++ b/plat/arm/board/fvp/fvp_common.c @@ -176,7 +176,7 @@ static unsigned int get_interconnect_master(void) u_register_t mpidr; mpidr = read_mpidr_el1(); - master = (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) ? + master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ? MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); assert(master < FVP_CLUSTER_COUNT); @@ -327,7 +327,7 @@ void __init fvp_config_setup(void) * affinities, is uniform across the platform: either all CPUs, or no * CPUs implement it. */ - if (read_mpidr_el1() & MPIDR_MT_MASK) + if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; } @@ -336,35 +336,31 @@ void __init fvp_interconnect_init(void) { #if FVP_INTERCONNECT_DRIVER == FVP_CCN if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { - ERROR("Unrecognized CCN variant detected. Only CCN-502" - " is supported"); + ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported"); panic(); } plat_arm_interconnect_init(); #else - uintptr_t cci_base = 0; - const int *cci_map = 0; - unsigned int map_size = 0; - - if (!(arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | - ARM_CONFIG_FVP_HAS_CCI5XX))) { - return; - } + uintptr_t cci_base = 0U; + const int *cci_map = NULL; + unsigned int map_size = 0U; /* Initialize the right interconnect */ - if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) { + if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) { cci_base = PLAT_FVP_CCI5XX_BASE; cci_map = fvp_cci5xx_map; map_size = ARRAY_SIZE(fvp_cci5xx_map); - } else if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) { + } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) { cci_base = PLAT_FVP_CCI400_BASE; cci_map = fvp_cci400_map; map_size = ARRAY_SIZE(fvp_cci400_map); + } else { + return; } - assert(cci_base); - assert(cci_map); + assert(cci_base != 0U); + assert(cci_map != NULL); cci_init(cci_base, cci_map, map_size); #endif } @@ -376,8 +372,8 @@ void fvp_interconnect_enable(void) #else unsigned int master; - if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | - ARM_CONFIG_FVP_HAS_CCI5XX)) { + if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | + ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { master = get_interconnect_master(); cci_enable_snoop_dvm_reqs(master); } @@ -391,8 +387,8 @@ void fvp_interconnect_disable(void) #else unsigned int master; - if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | - ARM_CONFIG_FVP_HAS_CCI5XX)) { + if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | + ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { master = get_interconnect_master(); cci_disable_snoop_dvm_reqs(master); } diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 44ab1b316..4fd4aef85 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -208,7 +208,7 @@ #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 /* System timer related constants */ -#define PLAT_ARM_NSTIMER_FRAME_ID 1 +#define PLAT_ARM_NSTIMER_FRAME_ID U(1) /* Mailbox base address */ #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index 89e28efb8..735e4a336 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -202,7 +202,7 @@ #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 /* System timer related constants */ -#define PLAT_ARM_NSTIMER_FRAME_ID 1 +#define PLAT_ARM_NSTIMER_FRAME_ID U(1) /* TZC related constants */ #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index 49f007402..b72dd201a 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -108,13 +108,13 @@ void arm_configure_sys_timer(void) unsigned int freq_val = plat_get_syscnt_freq2(); #if ARM_CONFIG_CNTACR - reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); - reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); - reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); + reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT); + reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT); + reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT); mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); #endif /* ARM_CONFIG_CNTACR */ - reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); + reg_val = (1U << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); /* @@ -154,7 +154,7 @@ unsigned int plat_get_syscnt_freq2(void) counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); /* The first entry of the frequency modes table must not be 0 */ - if (counter_base_frequency == 0) + if (counter_base_frequency == 0U) panic(); return counter_base_frequency; diff --git a/plat/arm/common/arm_err.c b/plat/arm/common/arm_err.c index 519d44d7d..aa65f4f33 100644 --- a/plat/arm/common/arm_err.c +++ b/plat/arm/common/arm_err.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -27,7 +28,7 @@ void __dead2 plat_arm_error_handler(int err) case -EAUTH: /* Image load or authentication error. Erase the ToC */ INFO("Erasing FIP ToC from flash...\n"); - nor_unlock(PLAT_ARM_FIP_BASE); + (void)nor_unlock(PLAT_ARM_FIP_BASE); ret = nor_word_program(PLAT_ARM_FIP_BASE, 0); if (ret != 0) { ERROR("Cannot erase ToC\n");