From a8834474033ecf73709b190d5f9e58df9c79f79d Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Tue, 16 Feb 2021 12:23:56 +0530 Subject: [PATCH 1/9] plat/sgi: refactor SDEI specific macros The macros specific to SDEI defined in the sgi_base_platform_def.h are not applicable for all the platforms supported by plat/sgi. So refactor the SDEI specific macros into a new header file and include this file on only on platforms it is applicable on. Signed-off-by: Thomas Abraham Change-Id: I0cb7125334f02a21cae1837cdfd765c16ab50bf5 --- .../arm/board/rde1edge/include/platform_def.h | 3 ++- .../arm/board/rdn1edge/include/platform_def.h | 3 ++- plat/arm/board/sgi575/include/platform_def.h | 3 ++- .../css/sgi/include/sgi_base_platform_def.h | 12 +-------- plat/arm/css/sgi/include/sgi_sdei.h | 25 +++++++++++++++++++ 5 files changed, 32 insertions(+), 14 deletions(-) create mode 100644 plat/arm/css/sgi/include/sgi_sdei.h diff --git a/plat/arm/board/rde1edge/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h index c39fe2b69..a9b30a41d 100644 --- a/plat/arm/board/rde1edge/include/platform_def.h +++ b/plat/arm/board/rde1edge/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, Arm Limited. All rights reserved. + * Copyright (c) 2018-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include +#include #include #define PLAT_ARM_CLUSTER_COUNT U(2) diff --git a/plat/arm/board/rdn1edge/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h index b167c46e0..a61b0d555 100644 --- a/plat/arm/board/rdn1edge/include/platform_def.h +++ b/plat/arm/board/rdn1edge/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include +#include #include #define PLAT_ARM_CLUSTER_COUNT U(2) diff --git a/plat/arm/board/sgi575/include/platform_def.h b/plat/arm/board/sgi575/include/platform_def.h index c929334cd..72d5f7cf0 100644 --- a/plat/arm/board/sgi575/include/platform_def.h +++ b/plat/arm/board/sgi575/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include +#include #include #define PLAT_ARM_CLUSTER_COUNT U(2) diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index b805746de..d99ea3bcd 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -183,16 +183,6 @@ #define SP_DMC_ERROR_ECC_EVENT_AARCH64 0xC4000044 #define SP_DMC_ERROR_ECC_EVENT_AARCH32 0x84000044 -/* ARM SDEI dynamic shared event numbers */ -#define SGI_SDEI_DS_EVENT_0 804 -#define SGI_SDEI_DS_EVENT_1 805 - -#define PLAT_ARM_PRIVATE_SDEI_EVENTS \ - SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ - SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_0, SDEI_MAPF_CRITICAL), \ - SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_1, SDEI_MAPF_CRITICAL), -#define PLAT_ARM_SHARED_SDEI_EVENTS - #define ARM_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ PLAT_SP_IMAGE_NS_BUF_SIZE) #define ARM_SP_CPER_BUF_SIZE ULL(0x20000) diff --git a/plat/arm/css/sgi/include/sgi_sdei.h b/plat/arm/css/sgi/include/sgi_sdei.h new file mode 100644 index 000000000..f380122bb --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_sdei.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGI_SDEI_H +#define SGI_SDEI_H + +#if SDEI_SUPPORT + +/* ARM SDEI dynamic shared event numbers */ +#define SGI_SDEI_DS_EVENT_0 U(804) +#define SGI_SDEI_DS_EVENT_1 U(805) + +#define PLAT_ARM_PRIVATE_SDEI_EVENTS \ + SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ + SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_0, SDEI_MAPF_CRITICAL), \ + SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_1, SDEI_MAPF_CRITICAL), + +#define PLAT_ARM_SHARED_SDEI_EVENTS + +#endif /* SDEI_SUPPORT */ + +#endif /* SGI_SDEI_H */ From 513ba5c97372dafb7bca60659e494e211413eedc Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Tue, 16 Feb 2021 12:24:13 +0530 Subject: [PATCH 2/9] plat/sgi: refactor DMC-620 error handling SMC function id The macros defining the SMC function ids for DMC-620 error handling are listed in the sgi_base_platform_def.h header file. But these macros are not applicable for all platforms supported under plat/sgi. So move these macro definitions to sgi_ras.c file in which these are consumed. While at it, remove the AArch32 and error injection function ids as these are unused. Signed-off-by: Thomas Abraham Change-Id: I249b54bf4c1b1694188a1e3b297345b942f16bc9 --- plat/arm/css/sgi/include/sgi_base_platform_def.h | 10 ---------- plat/arm/css/sgi/include/sgi_ras.h | 6 +++++- 2 files changed, 5 insertions(+), 11 deletions(-) diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index d99ea3bcd..a38c81187 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -173,16 +173,6 @@ PLAT_SP_IMAGE_NS_BUF_SIZE + \ PLAT_SP_BUF_BASE) -/* Platform specific SMC FID's used for RAS */ -#define SP_DMC_ERROR_INJECT_EVENT_AARCH64 0xC4000042 -#define SP_DMC_ERROR_INJECT_EVENT_AARCH32 0x84000042 - -#define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH64 0xC4000043 -#define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH32 0x84000043 - -#define SP_DMC_ERROR_ECC_EVENT_AARCH64 0xC4000044 -#define SP_DMC_ERROR_ECC_EVENT_AARCH32 0x84000044 - #define ARM_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ PLAT_SP_IMAGE_NS_BUF_SIZE) #define ARM_SP_CPER_BUF_SIZE ULL(0x20000) diff --git a/plat/arm/css/sgi/include/sgi_ras.h b/plat/arm/css/sgi/include/sgi_ras.h index a449eae26..4b8a0d182 100644 --- a/plat/arm/css/sgi/include/sgi_ras.h +++ b/plat/arm/css/sgi/include/sgi_ras.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,10 @@ #ifndef SGI_RAS_H #define SGI_RAS_H +/* Platform specific SMC FID's used for DMC-620 RAS error handling */ +#define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH64 0xC4000043 +#define SP_DMC_ERROR_ECC_EVENT_AARCH64 0xC4000044 + /* * Mapping the RAS interrupt with SDEI event number and the event * id used with Standalone MM code From d306eb801ebbaa8cf3324465092ac939e6b2d28d Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Tue, 16 Feb 2021 11:36:00 +0530 Subject: [PATCH 3/9] plat/sgi: improve macros defining cper buffer memory region Remove the 'ARM_' prefix from the macros defining the CPER buffer memory and replace it with 'CSS_SGI_' prefix. These macros are applicable only for platforms supported within plat/sgi. In addition to this, ensure that these macros are defined only if the RAS_EXTENSION build option is enabled. Signed-off-by: Thomas Abraham Change-Id: I44df42cded18d9d3a4cb13e5c990e9ab3194daee --- .../css/sgi/include/sgi_base_platform_def.h | 44 +++++++++++-------- plat/arm/css/sgi/sgi_plat.c | 6 ++- 2 files changed, 30 insertions(+), 20 deletions(-) diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index a38c81187..f6c56e8f0 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -165,28 +165,36 @@ #define PLAT_SP_PRI PLAT_RAS_PRI -#if RAS_EXTENSION -/* Allocate 128KB for CPER buffers */ -#define PLAT_SP_BUF_BASE ULL(0x20000) - -#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ - PLAT_SP_IMAGE_NS_BUF_SIZE + \ - PLAT_SP_BUF_BASE) - -#define ARM_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ - PLAT_SP_IMAGE_NS_BUF_SIZE) -#define ARM_SP_CPER_BUF_SIZE ULL(0x20000) -#define ARM_SP_CPER_BUF_MMAP MAP_REGION2( \ - ARM_SP_CPER_BUF_BASE, \ - ARM_SP_CPER_BUF_BASE, \ - ARM_SP_CPER_BUF_SIZE, \ - MT_RW_DATA | MT_NS | MT_USER, \ +#if SPM_MM && RAS_EXTENSION +/* + * CPER buffer memory of 128KB is reserved and it is placed adjacent to the + * memory shared between EL3 and S-EL0. + */ +#define CSS_SGI_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ + PLAT_SP_IMAGE_NS_BUF_SIZE) +#define CSS_SGI_SP_CPER_BUF_SIZE ULL(0x20000) +#define CSS_SGI_SP_CPER_BUF_MMAP MAP_REGION2( \ + CSS_SGI_SP_CPER_BUF_BASE, \ + CSS_SGI_SP_CPER_BUF_BASE, \ + CSS_SGI_SP_CPER_BUF_SIZE, \ + MT_RW_DATA | MT_NS | MT_USER, \ PAGE_SIZE) -#else +/* + * Secure partition stack follows right after the memory space reserved for + * CPER buffer memory. + */ +#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ + PLAT_SP_IMAGE_NS_BUF_SIZE + \ + CSS_SGI_SP_CPER_BUF_SIZE) +#elif SPM_MM +/* + * Secure partition stack follows right after the memory region that is shared + * between EL3 and S-EL0. + */ #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ PLAT_SP_IMAGE_NS_BUF_SIZE) -#endif /* RAS_EXTENSION */ +#endif /* SPM_MM && RAS_EXTENSION */ /* Platform ID address */ #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c index 39eb89eb8..118bd2261 100644 --- a/plat/arm/css/sgi/sgi_plat.c +++ b/plat/arm/css/sgi/sgi_plat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -81,7 +81,9 @@ const mmap_region_t plat_arm_secure_partition_mmap[] = { PLAT_ARM_SECURE_MAP_DEVICE, ARM_SP_IMAGE_MMAP, ARM_SP_IMAGE_NS_BUF_MMAP, - ARM_SP_CPER_BUF_MMAP, +#if RAS_EXTENSION + CSS_SGI_SP_CPER_BUF_MMAP, +#endif ARM_SP_IMAGE_RW_MMAP, ARM_SPM_BUF_EL0_MMAP, {0} From b4d548f141191703389a835d7812a154b7f14c46 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Tue, 16 Feb 2021 14:22:41 +0530 Subject: [PATCH 4/9] plat/sgi: define default list of memory regions for dmc620 tzc Define a default DMC-620 TZC memory region configuration and use it to specify the TZC memory regions on sgi575, rdn1edge and rde1edge platforms. The default DMC-620 TZC memory regions are defined considering the support for secure paritition as well. Signed-off-by: Thomas Abraham Change-Id: Iedee3e57d0d3de5b65321444da51ec990d3702db --- plat/arm/board/rde1edge/rde1edge_security.c | 10 ++---- plat/arm/board/rdn1edge/rdn1edge_security.c | 10 ++---- plat/arm/board/sgi575/sgi575_security.c | 11 ++---- .../css/sgi/include/sgi_dmc620_tzc_regions.h | 36 +++++++++++++++++++ 4 files changed, 45 insertions(+), 22 deletions(-) create mode 100644 plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h diff --git a/plat/arm/board/rde1edge/rde1edge_security.c b/plat/arm/board/rde1edge/rde1edge_security.c index 2123e0931..35f81d19f 100644 --- a/plat/arm/board/rde1edge/rde1edge_security.c +++ b/plat/arm/board/rde1edge/rde1edge_security.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,7 @@ #include #include -#include +#include uintptr_t rde1edge_dmc_base[] = { RDE1EDGE_DMC620_BASE0, @@ -20,11 +20,7 @@ static const tzc_dmc620_driver_data_t rde1edge_plat_driver_data = { }; static const tzc_dmc620_acc_addr_data_t rde1edge_acc_addr_data[] = { - { - .region_base = ARM_AP_TZC_DRAM1_BASE, - .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1, - .sec_attr = TZC_DMC620_REGION_S_RDWR - } + CSS_SGI_DMC620_TZC_REGIONS_DEF }; static const tzc_dmc620_config_data_t rde1edge_plat_config_data = { diff --git a/plat/arm/board/rdn1edge/rdn1edge_security.c b/plat/arm/board/rdn1edge/rdn1edge_security.c index ffa893524..49435329b 100644 --- a/plat/arm/board/rdn1edge/rdn1edge_security.c +++ b/plat/arm/board/rdn1edge/rdn1edge_security.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited. All rights reserved. + * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,7 @@ #include #include -#include +#include uintptr_t rdn1edge_dmc_base[] = { RDN1EDGE_DMC620_BASE0, @@ -20,11 +20,7 @@ static const tzc_dmc620_driver_data_t rdn1edge_plat_driver_data = { }; static const tzc_dmc620_acc_addr_data_t rdn1edge_acc_addr_data[] = { - { - .region_base = ARM_AP_TZC_DRAM1_BASE, - .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1, - .sec_attr = TZC_DMC620_REGION_S_RDWR - } + CSS_SGI_DMC620_TZC_REGIONS_DEF }; static const tzc_dmc620_config_data_t rdn1edge_plat_config_data = { diff --git a/plat/arm/board/sgi575/sgi575_security.c b/plat/arm/board/sgi575/sgi575_security.c index 440f18d55..17d07d1a1 100644 --- a/plat/arm/board/sgi575/sgi575_security.c +++ b/plat/arm/board/sgi575/sgi575_security.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,8 +7,7 @@ #include #include -#include -#include +#include uintptr_t sgi575_dmc_base[] = { SGI575_DMC620_BASE0, @@ -21,11 +20,7 @@ static const tzc_dmc620_driver_data_t sgi575_plat_driver_data = { }; static const tzc_dmc620_acc_addr_data_t sgi575_acc_addr_data[] = { - { - .region_base = ARM_AP_TZC_DRAM1_BASE, - .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1, - .sec_attr = TZC_DMC620_REGION_S_RDWR - } + CSS_SGI_DMC620_TZC_REGIONS_DEF }; static const tzc_dmc620_config_data_t sgi575_plat_config_data = { diff --git a/plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h b/plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h new file mode 100644 index 000000000..e93916318 --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGI_DMC620_TZC_REGIONS_H +#define SGI_DMC620_TZC_REGIONS_H + +#include + +#if SPM_MM +#define CSS_SGI_DMC620_TZC_REGIONS_DEF \ + { \ + .region_base = ARM_AP_TZC_DRAM1_BASE, \ + .region_top = PLAT_SP_IMAGE_NS_BUF_BASE - 1, \ + .sec_attr = TZC_DMC620_REGION_S_RDWR \ + }, { \ + .region_base = PLAT_SP_IMAGE_NS_BUF_BASE, \ + .region_top = PLAT_ARM_SP_IMAGE_STACK_BASE - 1, \ + .sec_attr = TZC_DMC620_REGION_S_NS_RDWR \ + }, { \ + .region_base = PLAT_ARM_SP_IMAGE_STACK_BASE, \ + .region_top = ARM_AP_TZC_DRAM1_END, \ + .sec_attr = TZC_DMC620_REGION_S_RDWR \ + } +#else +#define CSS_SGI_DMC620_TZC_REGIONS_DEF \ + { \ + .region_base = ARM_AP_TZC_DRAM1_BASE, \ + .region_top = ARM_AP_TZC_DRAM1_END, \ + .sec_attr = TZC_DMC620_REGION_S_RDWR \ + } +#endif /* SPM_MM */ + +#endif /* SGI_DMC620_TZC_REGIONS_H */ From 5dae6bc71c27fd135248bcd131dc637cf0ab4454 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Mon, 15 Feb 2021 14:14:59 +0530 Subject: [PATCH 5/9] plat/sgi: allow access to nor2 flash and system registers from s-el0 Allow the access of system registers and nor2 flash memory region from s-el0. This allows the secure parititions residing at s-el0 to access these memory regions. Signed-off-by: Thomas Abraham Change-Id: I3887a86770de806323fbde0d20fdc96eec6e0c3c --- .../css/sgi/include/sgi_base_platform_def.h | 2 +- .../css/sgi/include/sgi_soc_platform_def.h | 20 ++++++++++++++++++- .../css/sgi/include/sgi_soc_platform_def_v2.h | 20 ++++++++++++++++++- plat/arm/css/sgi/sgi_plat.c | 2 ++ 4 files changed, 41 insertions(+), 3 deletions(-) diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index f6c56e8f0..4187bdc77 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -32,7 +32,7 @@ # if SPM_MM # define PLAT_ARM_MMAP_ENTRIES 9 # define MAX_XLAT_TABLES 7 -# define PLAT_SP_IMAGE_MMAP_REGIONS 7 +# define PLAT_SP_IMAGE_MMAP_REGIONS 9 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 # else # define PLAT_ARM_MMAP_ENTRIES (5 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) diff --git a/plat/arm/css/sgi/include/sgi_soc_platform_def.h b/plat/arm/css/sgi/include/sgi_soc_platform_def.h index d7a839a52..405d62f12 100644 --- a/plat/arm/css/sgi/include/sgi_soc_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_soc_platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,4 +12,22 @@ #include #include +/* Map the System registers to access from S-EL0 */ +#define CSS_SYSTEMREG_DEVICE_BASE (0x1C010000) +#define CSS_SYSTEMREG_DEVICE_SIZE (0x00010000) +#define PLAT_ARM_SECURE_MAP_SYSTEMREG MAP_REGION_FLAT( \ + CSS_SYSTEMREG_DEVICE_BASE, \ + CSS_SYSTEMREG_DEVICE_SIZE, \ + (MT_DEVICE | MT_RW | \ + MT_SECURE | MT_USER)) + +/* Map the NOR2 Flash to access from S-EL0 */ +#define CSS_NOR2_FLASH_DEVICE_BASE (0x10000000) +#define CSS_NOR2_FLASH_DEVICE_SIZE (0x04000000) +#define PLAT_ARM_SECURE_MAP_NOR2 MAP_REGION_FLAT( \ + CSS_NOR2_FLASH_DEVICE_BASE, \ + CSS_NOR2_FLASH_DEVICE_SIZE, \ + (MT_DEVICE | MT_RW | \ + MT_SECURE | MT_USER)) + #endif /* SGI_SOC_PLATFORM_DEF_H */ diff --git a/plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h b/plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h index cb747c34a..20dd6825d 100644 --- a/plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h +++ b/plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,4 +10,22 @@ #include #include +/* Map the System registers to access from S-EL0 */ +#define CSS_SYSTEMREG_DEVICE_BASE (0x0C010000) +#define CSS_SYSTEMREG_DEVICE_SIZE (0x00010000) +#define PLAT_ARM_SECURE_MAP_SYSTEMREG MAP_REGION_FLAT( \ + CSS_SYSTEMREG_DEVICE_BASE, \ + CSS_SYSTEMREG_DEVICE_SIZE, \ + (MT_DEVICE | MT_RW | \ + MT_SECURE | MT_USER)) + +/* Map the NOR2 Flash to access from S-EL0 */ +#define CSS_NOR2_FLASH_DEVICE_BASE (0x001054000000) +#define CSS_NOR2_FLASH_DEVICE_SIZE (0x000004000000) +#define PLAT_ARM_SECURE_MAP_NOR2 MAP_REGION_FLAT( \ + CSS_NOR2_FLASH_DEVICE_BASE, \ + CSS_NOR2_FLASH_DEVICE_SIZE, \ + (MT_DEVICE | MT_RW | \ + MT_SECURE | MT_USER)) + #endif /* SGI_SOC_PLATFORM_DEF_V2_H */ diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c index 118bd2261..995d630c0 100644 --- a/plat/arm/css/sgi/sgi_plat.c +++ b/plat/arm/css/sgi/sgi_plat.c @@ -78,6 +78,8 @@ const mmap_region_t plat_arm_mmap[] = { #if SPM_MM && defined(IMAGE_BL31) const mmap_region_t plat_arm_secure_partition_mmap[] = { + PLAT_ARM_SECURE_MAP_SYSTEMREG, + PLAT_ARM_SECURE_MAP_NOR2, PLAT_ARM_SECURE_MAP_DEVICE, ARM_SP_IMAGE_MMAP, ARM_SP_IMAGE_NS_BUF_MMAP, From 05b5c4175b67f728feb5715b9fce463df2310b65 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Thu, 14 May 2020 17:00:07 +0530 Subject: [PATCH 6/9] plat/sgi: define memory regions for multi-chip platforms For multi-chip platforms, add a macro to define the memory regions on chip numbers >1 and its associated access permissions. These memory regions are marked with non-secure access. Signed-off-by: Aditya Angadi Change-Id: If3d6180fd8ea61f45147c39d3140d694abf06617 --- plat/arm/css/sgi/include/sgi_base_platform_def.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index 4187bdc77..aca70f1bf 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -226,4 +226,17 @@ /* Number of SCMI channels on the platform */ #define PLAT_ARM_SCMI_CHANNEL_COUNT CSS_SGI_CHIP_COUNT +/* + * Mapping definition of the TrustZone Controller for ARM SGI/RD platforms + * where both the DRAM regions are marked for non-secure access. This applies + * to multi-chip platforms. + */ +#define SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(n) \ + {CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE, \ + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END, \ + ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ + {CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE, \ + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END, \ + ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} + #endif /* SGI_BASE_PLATFORM_DEF_H */ From 21803491175d6be209a5b9db7b8d27f8174cd111 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 17 Feb 2021 18:39:32 +0530 Subject: [PATCH 7/9] plat/sgi: allow access to TZC controller on all chips On a multi-chip platform, the boot CPU on the first chip programs the TZC controllers on all the remote chips. Define a memory region map for the TZC controllers for all the remote chips and include it in the BL2 memory map table. In addition to this, for SPM_MM enabled multi-chip platforms, increase the number of mmap entries and xlat table counts for EL3 execution context as well because the shared RAM regions and GIC address space of remote chips are accessed. Signed-off-by: Aditya Angadi Change-Id: I6f0b5fd22f9f28046451e382eef7f1f9258d88f7 --- .../css/sgi/include/sgi_base_platform_def.h | 31 +++++++++++++++---- plat/arm/css/sgi/sgi_plat.c | 9 ++++++ 2 files changed, 34 insertions(+), 6 deletions(-) diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index aca70f1bf..6bcdabdd1 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -26,12 +26,15 @@ /* * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the - * plat_arm_mmap array defined for each BL stage. + * plat_arm_mmap array defined for each BL stage. In addition to that, on + * multi-chip platforms, address regions on each of the remote chips are + * also mapped. In BL31, for instance, three address regions on the remote + * chips are accessed - secure ram, css device and soc device regions. */ #if defined(IMAGE_BL31) # if SPM_MM -# define PLAT_ARM_MMAP_ENTRIES 9 -# define MAX_XLAT_TABLES 7 +# define PLAT_ARM_MMAP_ENTRIES (9 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) +# define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) # define PLAT_SP_IMAGE_MMAP_REGIONS 9 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 # else @@ -41,6 +44,17 @@ #elif defined(IMAGE_BL32) # define PLAT_ARM_MMAP_ENTRIES 8 # define MAX_XLAT_TABLES 5 +#elif defined(IMAGE_BL2) +# define PLAT_ARM_MMAP_ENTRIES (11 + (CSS_SGI_CHIP_COUNT - 1)) + +/* + * MAX_XLAT_TABLES entries need to be doubled because when the address width + * exceeds 40 bits an additional level of translation is required. In case of + * multichip platforms peripherals also fall into address space with width + * > 40 bits + * + */ +# define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 2)) #elif !USE_ROMLIB # define PLAT_ARM_MMAP_ENTRIES 11 # define MAX_XLAT_TABLES 7 @@ -69,12 +83,17 @@ /* * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a - * little space for growth. + * little space for growth. Additional 8KiB space is added per chip in + * order to accommodate the additional level of translation required for "TZC" + * peripheral access which lies in >4TB address space. + * */ #if TRUSTED_BOARD_BOOT -# define PLAT_ARM_MAX_BL2_SIZE 0x1D000 +# define PLAT_ARM_MAX_BL2_SIZE (0x1D000 + ((CSS_SGI_CHIP_COUNT - 1) * \ + 0x2000)) #else -# define PLAT_ARM_MAX_BL2_SIZE 0x14000 +# define PLAT_ARM_MAX_BL2_SIZE (0x14000 + ((CSS_SGI_CHIP_COUNT - 1) * \ + 0x2000)) #endif /* diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c index 995d630c0..20c52e9c5 100644 --- a/plat/arm/css/sgi/sgi_plat.c +++ b/plat/arm/css/sgi/sgi_plat.c @@ -49,6 +49,15 @@ const mmap_region_t plat_arm_mmap[] = { CSS_SGI_MAP_DEVICE, SOC_CSS_MAP_DEVICE, ARM_MAP_NS_DRAM1, +#if CSS_SGI_CHIP_COUNT > 1 + CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1), +#endif +#if CSS_SGI_CHIP_COUNT > 2 + CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2), +#endif +#if CSS_SGI_CHIP_COUNT > 3 + CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3), +#endif #if ARM_BL31_IN_DRAM ARM_MAP_BL31_SEC_DRAM, #endif From f97b57950203fd1deb01dfb77e8b0edcd6a30799 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Wed, 17 Feb 2021 18:46:22 +0530 Subject: [PATCH 8/9] board/rdv1mc: initialize tzc400 controllers A TZC400 controller is placed inline on DRAM channels and regulates the secure and non-secure accesses to both secure and non-secure regions of the DRAM memory. Configure each of the TZC controllers across the Chips. For use by secure software, configure the first chip's trustzone controller to protect the upper 16MB of the memory of the first DRAM block for secure accesses only. The other regions are configured for non-secure read write access. For all the remote chips, all the DRAM regions are allowed for non-secure read and write access. Signed-off-by: Aditya Angadi Change-Id: I809f27eccadfc23ea0ef64e2fd87f95eb8f195c1 --- plat/arm/board/rdv1mc/include/platform_def.h | 25 ++++++++- plat/arm/board/rdv1mc/platform.mk | 4 +- plat/arm/board/rdv1mc/rdv1mc_security.c | 56 +++++++++++++++++++- 3 files changed, 82 insertions(+), 3 deletions(-) diff --git a/plat/arm/board/rdv1mc/include/platform_def.h b/plat/arm/board/rdv1mc/include/platform_def.h index 112b2102b..12ce8063a 100644 --- a/plat/arm/board/rdv1mc/include/platform_def.h +++ b/plat/arm/board/rdv1mc/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,6 +20,29 @@ #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 +/* TZC Related Constants */ +#define PLAT_ARM_TZC_BASE UL(0x21830000) +#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ + (n * TZC400_OFFSET)) +#define TZC400_OFFSET UL(0x1000000) +#define TZC400_COUNT U(8) +#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) + +#define TZC_NSAID_ALL_AP U(0) +#define TZC_NSAID_PCI U(1) +#define TZC_NSAID_HDLCD0 U(2) +#define TZC_NSAID_CLCD U(7) +#define TZC_NSAID_AP U(9) +#define TZC_NSAID_VIRTIO U(15) + +#define PLAT_ARM_TZC_NS_DEV_ACCESS \ + (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \ + (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \ + (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \ + (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \ + (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \ + (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO)) + /* Virtual address used by dynamic mem_protect for chunk_base */ #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000) diff --git a/plat/arm/board/rdv1mc/platform.mk b/plat/arm/board/rdv1mc/platform.mk index 50728416a..fb057936a 100644 --- a/plat/arm/board/rdv1mc/platform.mk +++ b/plat/arm/board/rdv1mc/platform.mk @@ -1,4 +1,4 @@ -# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -23,6 +23,8 @@ BL1_SOURCES += ${SGI_CPU_SOURCES} \ BL2_SOURCES += ${RDV1MC_BASE}/rdv1mc_plat.c \ ${RDV1MC_BASE}/rdv1mc_security.c \ ${RDV1MC_BASE}/rdv1mc_err.c \ + drivers/arm/tzc/tzc400.c \ + plat/arm/common/arm_tzc400.c \ lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c diff --git a/plat/arm/board/rdv1mc/rdv1mc_security.c b/plat/arm/board/rdv1mc/rdv1mc_security.c index 541f800a8..adc0bf816 100644 --- a/plat/arm/board/rdv1mc/rdv1mc_security.c +++ b/plat/arm/board/rdv1mc/rdv1mc_security.c @@ -1,10 +1,64 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include +#include +#include + +/* TZC memory regions for the first chip */ +static const arm_tzc_regions_info_t tzc_regions[] = { + ARM_TZC_REGIONS_DEF, + {} +}; + +#if CSS_SGI_CHIP_COUNT > 1 +static const arm_tzc_regions_info_t tzc_regions_mc[][CSS_SGI_CHIP_COUNT - 1] = { + { + /* TZC memory regions for second chip */ + SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1), + {} + }, +#if CSS_SGI_CHIP_COUNT > 2 + { + /* TZC memory regions for third chip */ + SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2), + {} + }, +#endif +#if CSS_SGI_CHIP_COUNT > 3 + { + /* TZC memory regions for fourth chip */ + SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3), + {} + }, +#endif +}; +#endif /* CSS_SGI_CHIP_COUNT */ + /* Initialize the secure environment */ void plat_arm_security_setup(void) { + unsigned int i; + + INFO("Configuring TrustZone Controller for Chip 0\n"); + + for (i = 0; i < TZC400_COUNT; i++) { + arm_tzc400_setup(TZC400_BASE(i), tzc_regions); + } + +#if CSS_SGI_CHIP_COUNT > 1 + unsigned int j; + + for (i = 1; i < CSS_SGI_CHIP_COUNT; i++) { + INFO("Configuring TrustZone Controller for Chip %u\n", i); + + for (j = 0; j < TZC400_COUNT; j++) { + arm_tzc400_setup(CSS_SGI_REMOTE_CHIP_MEM_OFFSET(i) + + TZC400_BASE(j), tzc_regions_mc[i-1]); + } + } +#endif } From c0d55ef7c09383c45bda1e6177e6715e80fe49b8 Mon Sep 17 00:00:00 2001 From: Omkar Anand Kulkarni Date: Fri, 22 Jan 2021 12:58:08 +0530 Subject: [PATCH 9/9] plat/sgi: allow usage of secure partions on rdn2 platform Add the secure partition mmap table and the secure partition boot information to support secure partitions on RD-N2 platform. In addition to this, add the required memory region mapping for accessing the SoC peripherals from the secure partition. Signed-off-by: Omkar Anand Kulkarni Change-Id: I2c75760d6c8c3da3ff4885599be420e924aeaf3c --- .../css/sgi/include/sgi_base_platform_def.h | 2 +- plat/arm/css/sgi/include/sgi_soc_css_def_v2.h | 14 +++- plat/arm/css/sgi/sgi_plat_v2.c | 82 ++++++++++++++++++- 3 files changed, 95 insertions(+), 3 deletions(-) diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index 6bcdabdd1..d795f258e 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -36,7 +36,7 @@ # define PLAT_ARM_MMAP_ENTRIES (9 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) # define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) # define PLAT_SP_IMAGE_MMAP_REGIONS 9 -# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 +# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 11 # else # define PLAT_ARM_MMAP_ENTRIES (5 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) # define MAX_XLAT_TABLES (6 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) diff --git a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h index 03f107367..103dd9a7a 100644 --- a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h +++ b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -70,6 +70,18 @@ SOC_PLATFORM_PERIPH_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) +#if SPM_MM +/* + * Memory map definition for the platform peripheral memory region that is + * accessible from S-EL0 (with secure user mode access). + */ +#define SOC_PLATFORM_PERIPH_MAP_DEVICE_USER \ + MAP_REGION_FLAT( \ + SOC_PLATFORM_PERIPH_BASE, \ + SOC_PLATFORM_PERIPH_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE | MT_USER) +#endif + #define SOC_SYSTEM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \ SOC_SYSTEM_PERIPH_BASE, \ SOC_SYSTEM_PERIPH_SIZE, \ diff --git a/plat/arm/css/sgi/sgi_plat_v2.c b/plat/arm/css/sgi/sgi_plat_v2.c index a770255fc..131cdf2b5 100644 --- a/plat/arm/css/sgi/sgi_plat_v2.c +++ b/plat/arm/css/sgi/sgi_plat_v2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,10 @@ #include #include +#if SPM_MM +#include +#endif + /* * Table of regions for different BL stages to map using the MMU. */ @@ -41,6 +45,9 @@ const mmap_region_t plat_arm_mmap[] = { #if ARM_BL31_IN_DRAM ARM_MAP_BL31_SEC_DRAM, #endif +#if SPM_MM + ARM_SP_IMAGE_MMAP, +#endif #if TRUSTED_BOARD_BOOT && !BL2_AT_EL3 ARM_MAP_BL1_RW, #endif @@ -57,13 +64,86 @@ const mmap_region_t plat_arm_mmap[] = { CSS_SGI_MAP_DEVICE, SOC_PLATFORM_PERIPH_MAP_DEVICE, SOC_SYSTEM_PERIPH_MAP_DEVICE, +#if SPM_MM + ARM_SPM_BUF_EL3_MMAP, +#endif {0} }; +#if SPM_MM && defined(IMAGE_BL31) +const mmap_region_t plat_arm_secure_partition_mmap[] = { + PLAT_ARM_SECURE_MAP_SYSTEMREG, + PLAT_ARM_SECURE_MAP_NOR2, + SOC_PLATFORM_PERIPH_MAP_DEVICE_USER, + ARM_SP_IMAGE_MMAP, + ARM_SP_IMAGE_NS_BUF_MMAP, + ARM_SP_IMAGE_RW_MMAP, + ARM_SPM_BUF_EL0_MMAP, + {0} +}; +#endif /* SPM_MM && defined(IMAGE_BL31) */ #endif ARM_CASSERT_MMAP +#if SPM_MM && defined(IMAGE_BL31) +/* + * Boot information passed to a secure partition during initialisation. Linear + * indices in MP information will be filled at runtime. + */ +static spm_mm_mp_info_t sp_mp_info[] = { + [0] = {0x81000000, 0}, + [1] = {0x81010000, 0}, + [2] = {0x81020000, 0}, + [3] = {0x81030000, 0}, + [4] = {0x81040000, 0}, + [5] = {0x81050000, 0}, + [6] = {0x81060000, 0}, + [7] = {0x81070000, 0}, + [8] = {0x81080000, 0}, + [9] = {0x81090000, 0}, + [10] = {0x810a0000, 0}, + [11] = {0x810b0000, 0}, + [12] = {0x810c0000, 0}, + [13] = {0x810d0000, 0}, + [14] = {0x810e0000, 0}, + [15] = {0x810f0000, 0}, +}; + +const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { + .h.type = PARAM_SP_IMAGE_BOOT_INFO, + .h.version = VERSION_1, + .h.size = sizeof(spm_mm_boot_info_t), + .h.attr = 0, + .sp_mem_base = ARM_SP_IMAGE_BASE, + .sp_mem_limit = ARM_SP_IMAGE_LIMIT, + .sp_image_base = ARM_SP_IMAGE_BASE, + .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, + .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, + .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, + .sp_shared_buf_base = PLAT_SPM_BUF_BASE, + .sp_image_size = ARM_SP_IMAGE_SIZE, + .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, + .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, + .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, + .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, + .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, + .num_cpus = PLATFORM_CORE_COUNT, + .mp_info = &sp_mp_info[0], +}; + +const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) +{ + return plat_arm_secure_partition_mmap; +} + +const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( + void *cookie) +{ + return &plat_arm_secure_partition_boot_info; +} +#endif /* SPM_MM && defined(IMAGE_BL31) */ + #if TRUSTED_BOARD_BOOT int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) {