andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call 

The third argument of the reg_set() function has name 'mask', which
indicates that it is a mask applied to the register value which is
going to be updated. But the implementation of this function uses
this argument to clear prior value of the register, i.e. instead of
  new_val = (old_val & ~mask) | (data & mask);
it does
  new_val = (new_val & ~mask) | data;

(The more proper name for this function should be reg_clrsetbits(),
 since internally it calls mmio_clrsetbits_32().)

To make code more readable set 'mask' argument to real mask, i.e. bits
of register values which are going to be updated.

This patch does not make any functional change, only cosmetic, due to
how 'mask' is interpreted.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ifa0339e79c07d1994c7971b65d966b92cb735f65
This commit is contained in:
Pali Rohár 2021-03-24 16:40:46 +01:00
parent ee4c70ebb9
commit ccec1bd5ca
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/marvell/comphy/phy-comphy-3700.c
View File

@ -564,7 +564,7 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
* refer to RX initialization part for details.
*/
reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index),
PHY_RX_INIT_BIT, 0x0);
PHY_RX_INIT_BIT, PHY_RX_INIT_BIT);
ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE +
COMPHY_PHY_STATUS_OFFSET(comphy_index),
@ -595,7 +595,7 @@ static int mvebu_a3700_comphy_sgmii_power_off(uint8_t comphy_index)
debug_enter();
data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT;
mask = 0;
mask = data;
offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index);
reg_set(offset, data, mask);
@ -813,15 +813,15 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index,
/* 1. Enable max PLL. */
reg_set16(LANE_CFG1_ADDR(PCIE) + COMPHY_SD_ADDR,
USE_MAX_PLL_RATE_EN, 0x0);
USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN);
/* 2. Select 20 bit SERDES interface. */
reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR,
CFG_SEL_20B, 0);
CFG_SEL_20B, CFG_SEL_20B);
/* 3. Force to use reg setting for PCIe mode */
reg_set16(MISC_REG1_ADDR(PCIE) + COMPHY_SD_ADDR,
SEL_BITS_PCIE_FORCE, 0);
SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE);
/* 4. Change RX wait */
reg_set16(PWR_MGM_TIM1_ADDR(PCIE) + COMPHY_SD_ADDR,