Tegra194: Update wake mask, wake time for cpu offlining
This patch updates the wake mask and wake time to indicate to the mce/mts that the cpu is powering down. Wake time is set to highest possible value and wake mask is set to zero. Change-Id: Ic5abf15e7b98f911def6aa610d300b0668cd287e Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
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@ -216,11 +216,20 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
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/* Enable cluster powerdn from last CPU in the cluster */
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/* Enable cluster powerdn from last CPU in the cluster */
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if (cluster_powerdn) {
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if (cluster_powerdn) {
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/* Enable CC7 state and turn off wake mask */
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/* Enable CC6 */
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/* todo */
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/* If cluster group needs to be railgated, request CG7 */
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/* todo */
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/* Turn off wake mask */
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cstate_info.update_wake_mask = 1U;
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mce_update_cstate_info(&cstate_info);
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} else {
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} else {
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/* Turn off wake_mask */
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/* Turn off wake_mask */
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cstate_info.update_wake_mask = 1U;
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mce_update_cstate_info(&cstate_info);
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}
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}
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}
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}
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@ -347,12 +356,16 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
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int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
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{
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{
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int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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int32_t ret = 0;
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/* Disable Denver's DCO operations */
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/* Disable Denver's DCO operations */
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if (impl == DENVER_IMPL)
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if (impl == DENVER_IMPL)
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denver_disable_dco();
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denver_disable_dco();
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/* Turn off CPU */
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/* Turn off CPU */
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ret = mce_command_handler(MCE_CMD_ENTER_CSTATE,
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TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0);
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assert(ret == 0);
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return PSCI_E_SUCCESS;
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return PSCI_E_SUCCESS;
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}
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}
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