amlogic: g12a: Add support for the S905X2 (G12A) platform
Introduce the preliminary support for the Amlogic S905X2 (G12A) SoC. This port is a minimal implementation of BL31 capable of booting mainline U-Boot and Linux. Tested on a SEI510 board. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ife958f10e815a4530292c45446adb71239f3367f
This commit is contained in:
Carlo Caione
parent
edcadeb7b8
commit
cdb8c52f92
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@ -48,6 +48,14 @@ Amlogic Meson S905x (GXL) platform port
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:F: drivers/amlogic/gxl
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:F: plat/amlogic/gxl/
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Amlogic Meson S905X2 (G12A) platform port
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---------------------------------------
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:M: Carlo Caione <ccaione@baylibre.com>
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:G: `carlo.caione`_
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:F: docs/plat/meson-g12a.rst
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:F: drivers/amlogic/g12a
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:F: plat/amlogic/g12a/
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Armv7-A architecture port
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-------------------------
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:M: Etienne Carriere <etienne.carriere@linaro.org>
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@ -0,0 +1,27 @@
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Amlogic Meson S905X2 (G12A)
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==========================
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The Amlogic Meson S905X2 is a SoC with a quad core Arm Cortex-A53 running at
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~1.8GHz. It also contains a Cortex-M3 used as SCP.
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This port is a minimal implementation of BL31 capable of booting mainline U-Boot
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and Linux:
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- SCPI support.
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- Basic PSCI support (CPU_ON, CPU_OFF, SYSTEM_RESET, SYSTEM_OFF). Note that CPU0
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can't be turned off, so there is a workaround to hide this from the caller.
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- GICv2 driver set up.
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- Basic SIP services (read efuse data, enable/disable JTAG).
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In order to build it:
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.. code:: shell
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CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=g12a
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This port has been tested on a SEI510 board. After building it, follow the
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instructions in the `gxlimg repository` or `U-Boot repository`_, replacing the
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mentioned **bl31.img** by the one built from this port.
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.. _gxlimg repository: https://github.com/repk/gxlimg/blob/master/README.g12a
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.. _U-Boot repository: https://github.com/u-boot/u-boot/blob/master/board/amlogic/sei510/README
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@ -0,0 +1,142 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/bl_common.h>
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#include <common/interrupt_props.h>
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#include <drivers/arm/gicv2.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_mmu_helpers.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include "aml_private.h"
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/*
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* Placeholder variables for copying the arguments that have been passed to
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* BL31 from BL2.
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*/
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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static image_info_t bl30_image_info;
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static image_info_t bl301_image_info;
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image for
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* the security state specified. BL33 corresponds to the non-secure image type
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* while BL32 corresponds to the secure image type. A NULL pointer is returned
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* if the image does not exist.
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******************************************************************************/
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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next_image_info = (type == NON_SECURE) ?
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&bl33_image_ep_info : &bl32_image_ep_info;
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/* None of the images can have 0x0 as the entrypoint. */
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if (next_image_info->pc != 0U)
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return next_image_info;
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return NULL;
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}
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/*******************************************************************************
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* Perform any BL31 early platform setup. Here is an opportunity to copy
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* parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before
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* they are lost (potentially). This needs to be done before the MMU is
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* initialized so that the memory layout can be used while creating page
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* tables. BL2 has flushed this information to memory, so we are guaranteed
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* to pick up good data.
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******************************************************************************/
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struct g12a_bl31_param {
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param_header_t h;
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image_info_t *bl31_image_info;
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entry_point_info_t *bl32_ep_info;
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image_info_t *bl32_image_info;
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entry_point_info_t *bl33_ep_info;
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image_info_t *bl33_image_info;
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image_info_t *scp_image_info[];
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};
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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struct g12a_bl31_param *from_bl2;
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/* Initialize the console to provide early debug support */
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aml_console_init();
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from_bl2 = (struct g12a_bl31_param *)arg0;
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/* Check params passed from BL2 are not NULL. */
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assert(from_bl2 != NULL);
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assert(from_bl2->h.type == PARAM_BL31);
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assert(from_bl2->h.version >= VERSION_1);
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/*
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* Copy BL32 and BL33 entry point information. It is stored in Secure
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* RAM, in BL2's address space.
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*/
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bl32_image_ep_info = *from_bl2->bl32_ep_info;
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bl33_image_ep_info = *from_bl2->bl33_ep_info;
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if (bl33_image_ep_info.pc == 0U) {
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ERROR("BL31: BL33 entrypoint not obtained from BL2\n");
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panic();
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}
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bl30_image_info = *from_bl2->scp_image_info[0];
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bl301_image_info = *from_bl2->scp_image_info[1];
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}
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void bl31_plat_arch_setup(void)
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{
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aml_setup_page_tables();
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enable_mmu_el3(0);
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}
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/*******************************************************************************
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* GICv2 driver setup information
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******************************************************************************/
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static const interrupt_prop_t g12a_interrupt_props[] = {
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INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
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};
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static const gicv2_driver_data_t g12a_gic_data = {
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.gicd_base = AML_GICD_BASE,
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.gicc_base = AML_GICC_BASE,
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.interrupt_props = g12a_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(g12a_interrupt_props)
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};
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void bl31_platform_setup(void)
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{
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aml_mhu_secure_init();
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gicv2_driver_init(&g12a_gic_data);
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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@ -0,0 +1,125 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <bl31/interrupt_mgmt.h>
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#include <common/bl_common.h>
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#include <common/ep_info.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <platform_def.h>
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#include <stdint.h>
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/*******************************************************************************
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* Platform memory map regions
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******************************************************************************/
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#define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
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AML_NSDRAM0_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define MAP_NS_SHARE_MEM MAP_REGION_FLAT(AML_NS_SHARE_MEM_BASE, \
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AML_NS_SHARE_MEM_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define MAP_SEC_SHARE_MEM MAP_REGION_FLAT(AML_SEC_SHARE_MEM_BASE, \
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AML_SEC_SHARE_MEM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
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AML_SEC_DEVICE0_SIZE, \
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MT_DEVICE | MT_RW)
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#define MAP_HDCP_RX MAP_REGION_FLAT(AML_HDCP_RX_BASE, \
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AML_HDCP_RX_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_HDCP_TX MAP_REGION_FLAT(AML_HDCP_TX_BASE, \
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AML_HDCP_TX_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_GIC_DEVICE MAP_REGION_FLAT(AML_GIC_DEVICE_BASE, \
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AML_GIC_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
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AML_SEC_DEVICE1_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
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AML_SEC_DEVICE2_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
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AML_TZRAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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static const mmap_region_t g12a_mmap[] = {
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MAP_NSDRAM0,
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MAP_NS_SHARE_MEM,
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MAP_SEC_SHARE_MEM,
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MAP_SEC_DEVICE0,
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MAP_HDCP_RX,
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MAP_HDCP_TX,
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MAP_GIC_DEVICE,
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MAP_SEC_DEVICE1,
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MAP_SEC_DEVICE2,
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MAP_TZRAM,
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{0}
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};
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/*******************************************************************************
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* Per-image regions
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******************************************************************************/
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#define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \
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BL31_END - BL31_BASE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \
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BL_CODE_END - BL_CODE_BASE, \
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MT_CODE | MT_SECURE)
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#define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
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BL_RO_DATA_END - BL_RO_DATA_BASE, \
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MT_RO_DATA | MT_SECURE)
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#define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \
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BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/*******************************************************************************
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* Function that sets up the translation tables.
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******************************************************************************/
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void aml_setup_page_tables(void)
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{
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#if IMAGE_BL31
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const mmap_region_t g12a_bl_mmap[] = {
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MAP_BL31,
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MAP_BL_CODE,
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MAP_BL_RO_DATA,
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#if USE_COHERENT_MEM
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MAP_BL_COHERENT,
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#endif
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{0}
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};
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#endif
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mmap_add(g12a_bl_mmap);
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mmap_add(g12a_mmap);
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init_xlat_tables();
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}
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/*******************************************************************************
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* Function that returns the system counter frequency
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******************************************************************************/
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unsigned int plat_get_syscnt_freq2(void)
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{
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mmio_clrbits_32(AML_SYS_CPU_CFG7, ~0xFDFFFFFF);
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mmio_clrbits_32(AML_AO_TIMESTAMP_CNTL, ~0xFFFFFE00);
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return AML_OSC24M_CLK_IN_HZ;
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}
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@ -0,0 +1,135 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef G12A_DEF_H
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#define G12A_DEF_H
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#include <lib/utils_def.h>
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/*******************************************************************************
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* System oscillator
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******************************************************************************/
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#define AML_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */
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/*******************************************************************************
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* Memory regions
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******************************************************************************/
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#define AML_HDCP_RX_BASE UL(0xFFE0D000)
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#define AML_HDCP_RX_SIZE UL(0x00002000)
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#define AML_HDCP_TX_BASE UL(0xFFE01000)
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#define AML_HDCP_TX_SIZE UL(0x00001000)
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#define AML_NS_SHARE_MEM_BASE UL(0x05000000)
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#define AML_NS_SHARE_MEM_SIZE UL(0x00100000)
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#define AML_SEC_SHARE_MEM_BASE UL(0x05200000)
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#define AML_SEC_SHARE_MEM_SIZE UL(0x00100000)
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#define AML_GIC_DEVICE_BASE UL(0xFFC00000)
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#define AML_GIC_DEVICE_SIZE UL(0x00008000)
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#define AML_NSDRAM0_BASE UL(0x01000000)
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#define AML_NSDRAM0_SIZE UL(0x0F000000)
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#define BL31_BASE UL(0x05100000)
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#define BL31_SIZE UL(0x00100000)
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#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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/* Shared memory used for SMC services */
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#define AML_SHARE_MEM_INPUT_BASE UL(0x050FE000)
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#define AML_SHARE_MEM_OUTPUT_BASE UL(0x050FF000)
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#define AML_SEC_DEVICE0_BASE UL(0xFFD00000)
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#define AML_SEC_DEVICE0_SIZE UL(0x00026000)
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#define AML_SEC_DEVICE1_BASE UL(0xFF800000)
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#define AML_SEC_DEVICE1_SIZE UL(0x0000A000)
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#define AML_TZRAM_BASE UL(0xFFFA0000)
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#define AML_TZRAM_SIZE UL(0x00048000)
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/* Mailboxes */
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#define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xFFFE7800)
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#define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xFFFE7A00)
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#define AML_PSCI_MAILBOX_BASE UL(0xFFFE7F00)
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#define AML_SEC_DEVICE2_BASE UL(0xFF620000)
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#define AML_SEC_DEVICE2_SIZE UL(0x00028000)
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/*******************************************************************************
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* GIC-400 and interrupt handling related constants
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******************************************************************************/
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#define AML_GICD_BASE UL(0xFFC01000)
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#define AML_GICC_BASE UL(0xFFC02000)
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#define IRQ_SEC_PHY_TIMER 29
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#define IRQ_SEC_SGI_0 8
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#define IRQ_SEC_SGI_1 9
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#define IRQ_SEC_SGI_2 10
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#define IRQ_SEC_SGI_3 11
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#define IRQ_SEC_SGI_4 12
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#define IRQ_SEC_SGI_5 13
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#define IRQ_SEC_SGI_6 14
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#define IRQ_SEC_SGI_7 15
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#define IRQ_SEC_SGI_8 16
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/*******************************************************************************
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* UART definitions
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******************************************************************************/
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#define AML_UART0_AO_BASE UL(0xFF803000)
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#define AML_UART0_AO_CLK_IN_HZ AML_OSC24M_CLK_IN_HZ
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#define AML_UART_BAUDRATE U(115200)
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/*******************************************************************************
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* Memory-mapped I/O Registers
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******************************************************************************/
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#define AML_AO_TIMESTAMP_CNTL UL(0xFF8000B4)
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#define AML_SYS_CPU_CFG7 UL(0xFF634664)
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#define AML_AO_RTI_STATUS_REG3 UL(0xFF80001C)
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#define AML_AO_RTI_SCP_STAT UL(0xFF80023C)
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#define AML_AO_RTI_SCP_READY_OFF U(0x14)
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#define AML_A0_RTI_SCP_READY_MASK U(3)
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#define AML_AO_RTI_SCP_IS_READY(v) \
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((((v) >> AML_AO_RTI_SCP_READY_OFF) & \
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AML_A0_RTI_SCP_READY_MASK) == AML_A0_RTI_SCP_READY_MASK)
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#define AML_HIU_MAILBOX_SET_0 UL(0xFF63C404)
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#define AML_HIU_MAILBOX_STAT_0 UL(0xFF63C408)
|
||||
#define AML_HIU_MAILBOX_CLR_0 UL(0xFF63C40C)
|
||||
#define AML_HIU_MAILBOX_SET_3 UL(0xFF63C428)
|
||||
#define AML_HIU_MAILBOX_STAT_3 UL(0xFF63C42C)
|
||||
#define AML_HIU_MAILBOX_CLR_3 UL(0xFF63C430)
|
||||
|
||||
#define AML_SHA_DMA_BASE UL(0xFF63E000)
|
||||
#define AML_SHA_DMA_DESC (AML_SHA_DMA_BASE + 0x08)
|
||||
#define AML_SHA_DMA_STATUS (AML_SHA_DMA_BASE + 0x28)
|
||||
|
||||
/*******************************************************************************
|
||||
* System Monitor Call IDs and arguments
|
||||
******************************************************************************/
|
||||
#define AML_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020)
|
||||
#define AML_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021)
|
||||
|
||||
#define AML_SM_EFUSE_READ U(0x82000030)
|
||||
#define AML_SM_EFUSE_USER_MAX U(0x82000033)
|
||||
|
||||
#define AML_SM_JTAG_ON U(0x82000040)
|
||||
#define AML_SM_JTAG_OFF U(0x82000041)
|
||||
#define AML_SM_GET_CHIP_ID U(0x82000044)
|
||||
|
||||
#define AML_JTAG_STATE_ON U(0)
|
||||
#define AML_JTAG_STATE_OFF U(1)
|
||||
|
||||
#define AML_JTAG_M3_AO U(0)
|
||||
#define AML_JTAG_M3_EE U(1)
|
||||
#define AML_JTAG_A53_AO U(2)
|
||||
#define AML_JTAG_A53_EE U(3)
|
||||
|
||||
#endif /* G12A_DEF_H */
|
||||
|
|
@ -0,0 +1,215 @@
|
|||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <assert.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/arm/gicv2.h>
|
||||
#include <drivers/console.h>
|
||||
#include <errno.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/psci/psci.h>
|
||||
#include <plat/common/platform.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
#include "aml_private.h"
|
||||
|
||||
#define SCPI_POWER_ON 0
|
||||
#define SCPI_POWER_RETENTION 1
|
||||
#define SCPI_POWER_OFF 3
|
||||
|
||||
#define SCPI_SYSTEM_SHUTDOWN 0
|
||||
#define SCPI_SYSTEM_REBOOT 1
|
||||
|
||||
static uintptr_t g12a_sec_entrypoint;
|
||||
static volatile uint32_t g12a_cpu0_go;
|
||||
|
||||
static void g12a_pm_set_reset_addr(u_register_t mpidr, uint64_t value)
|
||||
{
|
||||
unsigned int core = plat_calc_core_pos(mpidr);
|
||||
uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4);
|
||||
|
||||
mmio_write_64(cpu_mailbox_addr, value);
|
||||
}
|
||||
|
||||
static void g12a_pm_reset(u_register_t mpidr)
|
||||
{
|
||||
unsigned int core = plat_calc_core_pos(mpidr);
|
||||
uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4) + 8;
|
||||
|
||||
mmio_write_32(cpu_mailbox_addr, 0);
|
||||
}
|
||||
|
||||
static void __dead2 g12a_system_reset(void)
|
||||
{
|
||||
INFO("BL31: PSCI_SYSTEM_RESET\n");
|
||||
|
||||
u_register_t mpidr = read_mpidr_el1();
|
||||
uint32_t status = mmio_read_32(AML_AO_RTI_STATUS_REG3);
|
||||
int ret;
|
||||
|
||||
NOTICE("BL31: Reboot reason: 0x%x\n", status);
|
||||
|
||||
status &= 0xFFFF0FF0;
|
||||
|
||||
console_flush();
|
||||
|
||||
mmio_write_32(AML_AO_RTI_STATUS_REG3, status);
|
||||
|
||||
ret = aml_scpi_sys_power_state(SCPI_SYSTEM_REBOOT);
|
||||
|
||||
if (ret != 0) {
|
||||
ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %i\n", ret);
|
||||
panic();
|
||||
}
|
||||
|
||||
g12a_pm_reset(mpidr);
|
||||
|
||||
wfi();
|
||||
|
||||
ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n");
|
||||
panic();
|
||||
}
|
||||
|
||||
static void __dead2 g12a_system_off(void)
|
||||
{
|
||||
INFO("BL31: PSCI_SYSTEM_OFF\n");
|
||||
|
||||
u_register_t mpidr = read_mpidr_el1();
|
||||
int ret;
|
||||
|
||||
ret = aml_scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
|
||||
|
||||
if (ret != 0) {
|
||||
ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %i\n", ret);
|
||||
panic();
|
||||
}
|
||||
|
||||
g12a_pm_set_reset_addr(mpidr, 0);
|
||||
g12a_pm_reset(mpidr);
|
||||
|
||||
wfi();
|
||||
|
||||
ERROR("BL31: PSCI_SYSTEM_OFF: Operation not handled\n");
|
||||
panic();
|
||||
}
|
||||
|
||||
static int32_t g12a_pwr_domain_on(u_register_t mpidr)
|
||||
{
|
||||
unsigned int core = plat_calc_core_pos(mpidr);
|
||||
|
||||
/* CPU0 can't be turned OFF */
|
||||
if (core == AML_PRIMARY_CPU) {
|
||||
VERBOSE("BL31: Releasing CPU0 from wait loop...\n");
|
||||
|
||||
g12a_cpu0_go = 1;
|
||||
flush_dcache_range((uintptr_t)&g12a_cpu0_go,
|
||||
sizeof(g12a_cpu0_go));
|
||||
dsb();
|
||||
isb();
|
||||
|
||||
sev();
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
g12a_pm_set_reset_addr(mpidr, g12a_sec_entrypoint);
|
||||
aml_scpi_set_css_power_state(mpidr,
|
||||
SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON);
|
||||
dmbsy();
|
||||
sev();
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
static void g12a_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
||||
{
|
||||
unsigned int core = plat_calc_core_pos(read_mpidr_el1());
|
||||
|
||||
assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
|
||||
PLAT_LOCAL_STATE_OFF);
|
||||
|
||||
if (core == AML_PRIMARY_CPU) {
|
||||
g12a_cpu0_go = 0;
|
||||
flush_dcache_range((uintptr_t)&g12a_cpu0_go,
|
||||
sizeof(g12a_cpu0_go));
|
||||
dsb();
|
||||
isb();
|
||||
}
|
||||
|
||||
gicv2_pcpu_distif_init();
|
||||
gicv2_cpuif_enable();
|
||||
}
|
||||
|
||||
static void g12a_pwr_domain_off(const psci_power_state_t *target_state)
|
||||
{
|
||||
u_register_t mpidr = read_mpidr_el1();
|
||||
unsigned int core = plat_calc_core_pos(mpidr);
|
||||
|
||||
gicv2_cpuif_disable();
|
||||
|
||||
/* CPU0 can't be turned OFF */
|
||||
if (core == AML_PRIMARY_CPU)
|
||||
return;
|
||||
|
||||
aml_scpi_set_css_power_state(mpidr,
|
||||
SCPI_POWER_OFF, SCPI_POWER_ON,
|
||||
SCPI_POWER_ON);
|
||||
}
|
||||
|
||||
static void __dead2 g12a_pwr_domain_pwr_down_wfi(const psci_power_state_t
|
||||
*target_state)
|
||||
{
|
||||
u_register_t mpidr = read_mpidr_el1();
|
||||
unsigned int core = plat_calc_core_pos(mpidr);
|
||||
|
||||
/* CPU0 can't be turned OFF, emulate it with a WFE loop */
|
||||
if (core == AML_PRIMARY_CPU) {
|
||||
VERBOSE("BL31: CPU0 entering wait loop...\n");
|
||||
|
||||
while (g12a_cpu0_go == 0)
|
||||
wfe();
|
||||
|
||||
VERBOSE("BL31: CPU0 resumed.\n");
|
||||
|
||||
/*
|
||||
* Because setting CPU0's warm reset entrypoint through PSCI
|
||||
* mailbox and/or mmio mapped RVBAR (0xda834650) does not seem
|
||||
* to work, jump to it manually.
|
||||
* In order to avoid an assert, MMU has to be disabled.
|
||||
*/
|
||||
disable_mmu_el3();
|
||||
((void(*)(void))g12a_sec_entrypoint)();
|
||||
}
|
||||
|
||||
dsbsy();
|
||||
g12a_pm_set_reset_addr(mpidr, 0);
|
||||
g12a_pm_reset(mpidr);
|
||||
|
||||
for (;;)
|
||||
wfi();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform handlers and setup function.
|
||||
******************************************************************************/
|
||||
static const plat_psci_ops_t g12a_ops = {
|
||||
.pwr_domain_on = g12a_pwr_domain_on,
|
||||
.pwr_domain_on_finish = g12a_pwr_domain_on_finish,
|
||||
.pwr_domain_off = g12a_pwr_domain_off,
|
||||
.pwr_domain_pwr_down_wfi = g12a_pwr_domain_pwr_down_wfi,
|
||||
.system_off = g12a_system_off,
|
||||
.system_reset = g12a_system_reset
|
||||
};
|
||||
|
||||
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
||||
const plat_psci_ops_t **psci_ops)
|
||||
{
|
||||
g12a_sec_entrypoint = sec_entrypoint;
|
||||
*psci_ops = &g12a_ops;
|
||||
g12a_cpu0_go = 0;
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
||||
|
||||
#include <arch.h>
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#include "../g12a_def.h"
|
||||
|
||||
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
|
||||
#define PLATFORM_LINKER_ARCH aarch64
|
||||
|
||||
#define PLATFORM_STACK_SIZE UL(0x1000)
|
||||
|
||||
#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
|
||||
#define PLATFORM_CLUSTER_COUNT U(1)
|
||||
#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
|
||||
#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
|
||||
|
||||
#define AML_PRIMARY_CPU U(0)
|
||||
|
||||
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
|
||||
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
|
||||
PLATFORM_CORE_COUNT)
|
||||
|
||||
#define PLAT_MAX_RET_STATE U(1)
|
||||
#define PLAT_MAX_OFF_STATE U(2)
|
||||
|
||||
/* Local power state for power domains in Run state. */
|
||||
#define PLAT_LOCAL_STATE_RUN U(0)
|
||||
/* Local power state for retention. Valid only for CPU power domains */
|
||||
#define PLAT_LOCAL_STATE_RET U(1)
|
||||
/* Local power state for power-down. Valid for CPU and cluster power domains. */
|
||||
#define PLAT_LOCAL_STATE_OFF U(2)
|
||||
|
||||
/*
|
||||
* Macros used to parse state information from State-ID if it is using the
|
||||
* recommended encoding for State-ID.
|
||||
*/
|
||||
#define PLAT_LOCAL_PSTATE_WIDTH U(4)
|
||||
#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1)
|
||||
|
||||
/*
|
||||
* Some data must be aligned on the biggest cache line size in the platform.
|
||||
* This is known only to the platform as it might have a combination of
|
||||
* integrated and external caches.
|
||||
*/
|
||||
#define CACHE_WRITEBACK_SHIFT U(6)
|
||||
#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
|
||||
|
||||
/* Memory-related defines */
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
|
||||
|
||||
#define MAX_MMAP_REGIONS 16
|
||||
#define MAX_XLAT_TABLES 8
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
#
|
||||
# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
include lib/xlat_tables_v2/xlat_tables.mk
|
||||
|
||||
AML_PLAT := plat/amlogic
|
||||
AML_PLAT_SOC := ${AML_PLAT}/${PLAT}
|
||||
AML_PLAT_COMMON := ${AML_PLAT}/common
|
||||
|
||||
DOIMAGEPATH ?= tools/amlogic
|
||||
DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage
|
||||
|
||||
PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \
|
||||
-I${AML_PLAT_SOC}/include \
|
||||
-I${AML_PLAT_COMMON}/include
|
||||
|
||||
GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
|
||||
drivers/arm/gic/v2/gicv2_main.c \
|
||||
drivers/arm/gic/v2/gicv2_helpers.c \
|
||||
plat/common/plat_gicv2.c
|
||||
|
||||
BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
|
||||
plat/common/plat_psci_common.c \
|
||||
drivers/amlogic/console/aarch64/meson_console.S \
|
||||
${AML_PLAT_SOC}/${PLAT}_bl31_setup.c \
|
||||
${AML_PLAT_SOC}/${PLAT}_pm.c \
|
||||
${AML_PLAT_SOC}/${PLAT}_common.c \
|
||||
${AML_PLAT_COMMON}/aarch64/aml_helpers.S \
|
||||
${AML_PLAT_COMMON}/aml_efuse.c \
|
||||
${AML_PLAT_COMMON}/aml_mhu.c \
|
||||
${AML_PLAT_COMMON}/aml_scpi.c \
|
||||
${AML_PLAT_COMMON}/aml_sip_svc.c \
|
||||
${AML_PLAT_COMMON}/aml_thermal.c \
|
||||
${AML_PLAT_COMMON}/aml_topology.c \
|
||||
${AML_PLAT_COMMON}/aml_console.c \
|
||||
drivers/amlogic/crypto/sha_dma.c \
|
||||
${XLAT_TABLES_LIB_SRCS} \
|
||||
${GIC_SOURCES}
|
||||
|
||||
# Tune compiler for Cortex-A53
|
||||
ifeq ($(notdir $(CC)),armclang)
|
||||
TF_CFLAGS_aarch64 += -mcpu=cortex-a53
|
||||
else ifneq ($(findstring clang,$(notdir $(CC))),)
|
||||
TF_CFLAGS_aarch64 += -mcpu=cortex-a53
|
||||
else
|
||||
TF_CFLAGS_aarch64 += -mtune=cortex-a53
|
||||
endif
|
||||
|
||||
# Build config flags
|
||||
# ------------------
|
||||
|
||||
# Enable all errata workarounds for Cortex-A53
|
||||
ERRATA_A53_855873 := 1
|
||||
ERRATA_A53_819472 := 1
|
||||
ERRATA_A53_824069 := 1
|
||||
ERRATA_A53_827319 := 1
|
||||
|
||||
WORKAROUND_CVE_2017_5715 := 0
|
||||
|
||||
# Have different sections for code and rodata
|
||||
SEPARATE_CODE_AND_RODATA := 1
|
||||
|
||||
# Use Coherent memory
|
||||
USE_COHERENT_MEM := 1
|
||||
|
||||
# Verify build config
|
||||
# -------------------
|
||||
|
||||
ifneq (${RESET_TO_BL31}, 0)
|
||||
$(error Error: ${PLAT} needs RESET_TO_BL31=0)
|
||||
endif
|
||||
|
||||
ifeq (${ARCH},aarch32)
|
||||
$(error Error: AArch32 not supported on ${PLAT})
|
||||
endif
|
||||
|
||||
all: ${BUILD_PLAT}/bl31.img
|
||||
distclean realclean clean: cleanimage
|
||||
|
||||
cleanimage:
|
||||
${Q}${MAKE} -C ${DOIMAGEPATH} clean
|
||||
|
||||
${DOIMAGETOOL}:
|
||||
${Q}${MAKE} -C ${DOIMAGEPATH}
|
||||
|
||||
${BUILD_PLAT}/bl31.img: ${BUILD_PLAT}/bl31.bin ${DOIMAGETOOL}
|
||||
${DOIMAGETOOL} ${BUILD_PLAT}/bl31.bin ${BUILD_PLAT}/bl31.img
|
||||
|
||||
Loading…
Reference in New Issue