plat: marvell: armada: re-enable BL32_BASE definition
As a preparation to support proper loading the OPTEE OS image, enable the BL32 specific defines in case the SPD is used. On the occasion move two BL32-related macros to marvell_def.h and fix BL32_LIMIT definition. Change-Id: Id4e2d81833bc1895650cca8b0fc0bfc341cf77f3 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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@ -173,5 +173,15 @@
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#define BL31_LIMIT (MARVELL_BL_RAM_BASE + \
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#define BL31_LIMIT (MARVELL_BL_RAM_BASE + \
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MARVELL_BL_RAM_SIZE)
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MARVELL_BL_RAM_SIZE)
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/*****************************************************************************
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* BL32 specific defines.
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*****************************************************************************
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*/
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#define BL32_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE
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#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_DRAM_SIZE)
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#ifdef SPD_none
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#undef BL32_BASE
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#endif /* SPD_none */
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#endif /* MARVELL_DEF_H */
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#endif /* MARVELL_DEF_H */
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@ -177,5 +177,14 @@
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#define BL31_LIMIT (MARVELL_BL_RAM_BASE + \
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#define BL31_LIMIT (MARVELL_BL_RAM_BASE + \
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MARVELL_BL_RAM_SIZE)
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MARVELL_BL_RAM_SIZE)
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/*******************************************************************************
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* BL32 specific defines.
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******************************************************************************/
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#define BL32_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE
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#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_DRAM_SIZE)
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#ifdef SPD_none
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#undef BL32_BASE
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#endif /* SPD_none */
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#endif /* MARVELL_DEF_H */
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#endif /* MARVELL_DEF_H */
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@ -221,12 +221,4 @@
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/* Securities */
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/* Securities */
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#define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER
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#define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER
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#define TRUSTED_DRAM_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE
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#define TRUSTED_DRAM_SIZE PLAT_MARVELL_TRUSTED_DRAM_SIZE
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#ifdef BL32
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#define BL32_BASE TRUSTED_DRAM_BASE
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#define BL32_LIMIT TRUSTED_DRAM_SIZE
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#endif
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#endif /* PLATFORM_DEF_H */
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#endif /* PLATFORM_DEF_H */
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@ -190,14 +190,6 @@
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/* Securities */
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/* Securities */
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#define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER
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#define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER
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#define TRUSTED_DRAM_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE
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#define TRUSTED_DRAM_SIZE PLAT_MARVELL_TRUSTED_DRAM_SIZE
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#ifdef BL32
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#define BL32_BASE TRUSTED_DRAM_BASE
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#define BL32_LIMIT TRUSTED_DRAM_SIZE
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#endif
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#define MVEBU_PMU_IRQ_WA
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#define MVEBU_PMU_IRQ_WA
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#endif /* PLATFORM_DEF_H */
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#endif /* PLATFORM_DEF_H */
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