From cf85030efe73439e06295f8185b0a6bebf7b5eae Mon Sep 17 00:00:00 2001 From: sahil Date: Tue, 15 Mar 2022 14:11:43 +0530 Subject: [PATCH] feat(n1sdp): add support for nt_fw_config This patch adds support to load nt_fw_config with the information from plat_info sds structure which is then passed from BL2 to BL33. Signed-off-by: sahil Change-Id: I2fcf13b7bf5ab042ef830157fd9cceedbdca617a --- plat/arm/board/n1sdp/fdts/n1sdp_fw_config.dts | 6 + .../board/n1sdp/fdts/n1sdp_nt_fw_config.dts | 23 +++ plat/arm/board/n1sdp/n1sdp_bl31_setup.c | 8 - plat/arm/board/n1sdp/n1sdp_def.h | 3 - plat/arm/board/n1sdp/n1sdp_image_load.c | 143 ++++++++++++++++++ plat/arm/board/n1sdp/platform.mk | 9 +- 6 files changed, 179 insertions(+), 13 deletions(-) create mode 100644 plat/arm/board/n1sdp/fdts/n1sdp_nt_fw_config.dts create mode 100644 plat/arm/board/n1sdp/n1sdp_image_load.c diff --git a/plat/arm/board/n1sdp/fdts/n1sdp_fw_config.dts b/plat/arm/board/n1sdp/fdts/n1sdp_fw_config.dts index 05358220e..f61e30bc5 100644 --- a/plat/arm/board/n1sdp/fdts/n1sdp_fw_config.dts +++ b/plat/arm/board/n1sdp/fdts/n1sdp_fw_config.dts @@ -15,5 +15,11 @@ max-size = <0x200>; id = ; }; + + nt_fw-config { + load-address = <0x0 0xFEF00000>; + max-size = <0x0100000>; + id = ; + }; }; }; diff --git a/plat/arm/board/n1sdp/fdts/n1sdp_nt_fw_config.dts b/plat/arm/board/n1sdp/fdts/n1sdp_nt_fw_config.dts new file mode 100644 index 000000000..da5e04ddb --- /dev/null +++ b/plat/arm/board/n1sdp/fdts/n1sdp_nt_fw_config.dts @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/dts-v1/; +/ { + /* compatible string */ + compatible = "arm,n1sdp"; + + /* + * Place holder for platform-info node with default values. + * The values will be set to the correct values during + * the BL2 stage of boot. + */ + platform-info { + multichip-mode = <0x0>; + secondary-chip-count = <0x0>; + local-ddr-size = <0x0>; + remote-ddr-size = <0x0>; + }; +}; \ No newline at end of file diff --git a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c index e52a762b7..5e897fee3 100644 --- a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c +++ b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c @@ -158,12 +158,4 @@ void bl31_platform_setup(void) /* Check if remote memory is present */ if ((plat_info.multichip_mode) && (plat_info.remote_ddr_size != 0)) remote_dmc_ecc_setup(plat_info.remote_ddr_size); - /* - * Pass platform information to BL33. This method is followed as - * currently there is no BL1/BL2 involved in boot flow of N1SDP. - * When TBBR is implemented for N1SDP, this method should be removed - * and platform information should be passed to BL33 using NT_FW_CONFIG - * passing mechanism. - */ - mmio_write_32(N1SDP_PLATFORM_INFO_BASE, *(uint32_t *)&plat_info); } diff --git a/plat/arm/board/n1sdp/n1sdp_def.h b/plat/arm/board/n1sdp/n1sdp_def.h index 482ad570d..ffa6a03e8 100644 --- a/plat/arm/board/n1sdp/n1sdp_def.h +++ b/plat/arm/board/n1sdp/n1sdp_def.h @@ -49,7 +49,4 @@ /* DMC ECC enable bit in ERR0CTLR0 register */ #define N1SDP_DMC_ERR0CTLR0_ECC_EN 0x1 -/* Base address of non-secure SRAM where Platform information will be filled */ -#define N1SDP_PLATFORM_INFO_BASE 0x06008000 - #endif /* N1SDP_DEF_H */ diff --git a/plat/arm/board/n1sdp/n1sdp_image_load.c b/plat/arm/board/n1sdp/n1sdp_image_load.c new file mode 100644 index 000000000..6c3528ce8 --- /dev/null +++ b/plat/arm/board/n1sdp/n1sdp_image_load.c @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +#include "n1sdp_def.h" +#include + +/* + * Platform information structure stored in SDS. + * This structure holds information about platform's DDR + * size which will be used to zero out the memory before + * enabling the ECC capability as well as information + * about multichip setup + * - multichip mode + * - secondary_count + * - Local DDR size in GB, DDR memory in master board + * - Remote DDR size in GB, DDR memory in secondary board + */ +struct n1sdp_plat_info { + bool multichip_mode; + uint8_t secondary_count; + uint8_t local_ddr_size; + uint8_t remote_ddr_size; +} __packed; + +/******************************************************************************* + * This function inserts Platform information via device tree nodes as, + * platform-info { + * multichip-mode = <0x0>; + * secondary-chip-count = <0x0>; + * local-ddr-size = <0x0>; + * remote-ddr-size = <0x0>; + * }; + ******************************************************************************/ +static int plat_n1sdp_append_config_node(struct n1sdp_plat_info *plat_info) +{ + bl_mem_params_node_t *mem_params; + void *fdt; + int nodeoffset, err; + + mem_params = get_bl_mem_params_node(NT_FW_CONFIG_ID); + if (mem_params == NULL) { + ERROR("NT_FW CONFIG base address is NULL\n"); + return -1; + } + + fdt = (void *)(mem_params->image_info.image_base); + + /* Check the validity of the fdt */ + if (fdt_check_header(fdt) != 0) { + ERROR("Invalid NT_FW_CONFIG DTB passed\n"); + return -1; + } + + nodeoffset = fdt_subnode_offset(fdt, 0, "platform-info"); + if (nodeoffset < 0) { + ERROR("NT_FW_CONFIG: Failed to get platform-info node offset\n"); + return -1; + } + + err = fdt_setprop_u32(fdt, nodeoffset, "multichip-mode", + plat_info->multichip_mode); + if (err < 0) { + ERROR("NT_FW_CONFIG: Failed to set multichip-mode\n"); + return -1; + } + + err = fdt_setprop_u32(fdt, nodeoffset, "secondary-chip-count", + plat_info->secondary_count); + if (err < 0) { + ERROR("NT_FW_CONFIG: Failed to set secondary-chip-count\n"); + return -1; + } + + err = fdt_setprop_u32(fdt, nodeoffset, "local-ddr-size", + plat_info->local_ddr_size); + if (err < 0) { + ERROR("NT_FW_CONFIG: Failed to set local-ddr-size\n"); + return -1; + } + + err = fdt_setprop_u32(fdt, nodeoffset, "remote-ddr-size", + plat_info->remote_ddr_size); + if (err < 0) { + ERROR("NT_FW_CONFIG: Failed to set remote-ddr-size\n"); + return -1; + } + + flush_dcache_range((uintptr_t)fdt, mem_params->image_info.image_size); + + return 0; +} + +/******************************************************************************* + * This function returns the list of executable images. + ******************************************************************************/ +bl_params_t *plat_get_next_bl_params(void) +{ + int ret; + struct n1sdp_plat_info plat_info; + + ret = sds_init(); + if (ret != SDS_OK) { + ERROR("SDS initialization failed. ret:%d\n", ret); + panic(); + } + + ret = sds_struct_read(N1SDP_SDS_PLATFORM_INFO_STRUCT_ID, + N1SDP_SDS_PLATFORM_INFO_OFFSET, + &plat_info, + N1SDP_SDS_PLATFORM_INFO_SIZE, + SDS_ACCESS_MODE_NON_CACHED); + if (ret != SDS_OK) { + ERROR("Error getting platform info from SDS. ret:%d\n", ret); + panic(); + } + + /* Validate plat_info SDS */ + if ((plat_info.local_ddr_size == 0U) + || (plat_info.local_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB) + || (plat_info.remote_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB) + || (plat_info.secondary_count > N1SDP_MAX_SECONDARY_COUNT) + ){ + ERROR("platform info SDS is corrupted\n"); + panic(); + } + + ret = plat_n1sdp_append_config_node(&plat_info); + if (ret != 0) { + panic(); + } + + return arm_get_next_bl_params(); +} diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk index 7eac4d22b..740fb2988 100644 --- a/plat/arm/board/n1sdp/platform.mk +++ b/plat/arm/board/n1sdp/platform.mk @@ -40,6 +40,7 @@ BL2_SOURCES := ${N1SDP_BASE}/n1sdp_security.c \ ${N1SDP_BASE}/n1sdp_trusted_boot.c \ lib/utils/mem_region.c \ ${N1SDP_BASE}/n1sdp_bl2_setup.c \ + ${N1SDP_BASE}/n1sdp_image_load.c \ drivers/arm/css/sds/sds.c BL31_SOURCES := ${N1SDP_CPU_SOURCES} \ @@ -52,16 +53,20 @@ BL31_SOURCES := ${N1SDP_CPU_SOURCES} \ FDT_SOURCES += fdts/${PLAT}-single-chip.dts \ fdts/${PLAT}-multi-chip.dts \ - ${N1SDP_BASE}/fdts/n1sdp_fw_config.dts \ - ${N1SDP_BASE}/fdts/n1sdp_tb_fw_config.dts + ${N1SDP_BASE}/fdts/n1sdp_fw_config.dts \ + ${N1SDP_BASE}/fdts/n1sdp_tb_fw_config.dts \ + ${N1SDP_BASE}/fdts/n1sdp_nt_fw_config.dts FW_CONFIG := ${BUILD_PLAT}/fdts/n1sdp_fw_config.dtb TB_FW_CONFIG := ${BUILD_PLAT}/fdts/n1sdp_tb_fw_config.dtb +NT_FW_CONFIG := ${BUILD_PLAT}/fdts/n1sdp_nt_fw_config.dtb # Add the FW_CONFIG to FIP and specify the same to certtool $(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) # Add the TB_FW_CONFIG to FIP and specify the same to certtool $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) +# Add the NT_FW_CONFIG to FIP and specify the same to certtool +$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG})) # Setting to 0 as no NVCTR in N1SDP N1SDP_FW_NVCTR_VAL := 0