From cfde1870ca713f2a89a80df80badd5805304103e Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Mon, 2 Mar 2020 22:15:08 +0800 Subject: [PATCH] hikey960: Enable system power off callback On Hikey960 if outputs GPIO176 low level, it can tell PMIC to power off the whole board. To avoid resetting the board and stay off, it also requires the SW2201's three switches 1/2/3 need to be all set to 0. Since current code doesn't contain complete GPIO modules and misses to support GPIO176. This patch adds all known GPIO modules and initialize GPIO in BL31, and adds system power off callback to use GPIO176 for PMIC power off operation. Change-Id: Ia88859b8b7c87c061420ef75f0de3e2768667bb0 Signed-off-by: Leo Yan --- plat/hisilicon/hikey960/hikey960_bl31_setup.c | 1 + plat/hisilicon/hikey960/hikey960_bl_common.c | 7 +++++++ plat/hisilicon/hikey960/hikey960_pm.c | 10 +++++++++- plat/hisilicon/hikey960/include/hi3660.h | 7 +++++++ plat/hisilicon/hikey960/platform.mk | 5 ++++- 5 files changed, 28 insertions(+), 2 deletions(-) diff --git a/plat/hisilicon/hikey960/hikey960_bl31_setup.c b/plat/hisilicon/hikey960/hikey960_bl31_setup.c index d3b4e4f68..f5f8ffed0 100644 --- a/plat/hisilicon/hikey960/hikey960_bl31_setup.c +++ b/plat/hisilicon/hikey960/hikey960_bl31_setup.c @@ -166,6 +166,7 @@ void bl31_platform_setup(void) hikey960_edma_init(); hikey960_iomcu_dma_init(); + hikey960_gpio_init(); hisi_ipc_init(); } diff --git a/plat/hisilicon/hikey960/hikey960_bl_common.c b/plat/hisilicon/hikey960/hikey960_bl_common.c index 89adccb2b..3c4a164ff 100644 --- a/plat/hisilicon/hikey960/hikey960_bl_common.c +++ b/plat/hisilicon/hikey960/hikey960_bl_common.c @@ -466,6 +466,13 @@ void hikey960_gpio_init(void) pl061_gpio_register(GPIO19_BASE, 19); pl061_gpio_register(GPIO20_BASE, 20); pl061_gpio_register(GPIO21_BASE, 21); + pl061_gpio_register(GPIO22_BASE, 22); + pl061_gpio_register(GPIO23_BASE, 23); + pl061_gpio_register(GPIO24_BASE, 24); + pl061_gpio_register(GPIO25_BASE, 25); + pl061_gpio_register(GPIO26_BASE, 26); + pl061_gpio_register(GPIO27_BASE, 27); + pl061_gpio_register(GPIO28_BASE, 28); /* PCIE_PERST_N output low */ gpio_set_direction(89, GPIO_DIR_OUT); diff --git a/plat/hisilicon/hikey960/hikey960_pm.c b/plat/hisilicon/hikey960/hikey960_pm.c index 9f96fc398..f836508d5 100644 --- a/plat/hisilicon/hikey960/hikey960_pm.c +++ b/plat/hisilicon/hikey960/hikey960_pm.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -116,6 +117,13 @@ void hikey960_pwr_domain_off(const psci_power_state_t *target_state) } } +static void __dead2 hikey960_system_off(void) +{ + gpio_set_direction(176, GPIO_DIR_OUT); + gpio_set_value(176, GPIO_LEVEL_LOW); + panic(); +} + static void __dead2 hikey960_system_reset(void) { dsb(); @@ -293,7 +301,7 @@ static const plat_psci_ops_t hikey960_psci_ops = { .pwr_domain_off = hikey960_pwr_domain_off, .pwr_domain_suspend = hikey960_pwr_domain_suspend, .pwr_domain_suspend_finish = hikey960_pwr_domain_suspend_finish, - .system_off = NULL, + .system_off = hikey960_system_off, .system_reset = hikey960_system_reset, .validate_power_state = hikey960_validate_power_state, .validate_ns_entrypoint = hikey960_validate_ns_entrypoint, diff --git a/plat/hisilicon/hikey960/include/hi3660.h b/plat/hisilicon/hikey960/include/hi3660.h index 7cc1ee0b8..17b495f21 100644 --- a/plat/hisilicon/hikey960/include/hi3660.h +++ b/plat/hisilicon/hikey960/include/hi3660.h @@ -260,6 +260,13 @@ #define GPIO17_BASE UL(0xE8A1C000) #define GPIO20_BASE UL(0xE8A1F000) #define GPIO21_BASE UL(0xE8A20000) +#define GPIO22_BASE UL(0xFFF0B000) +#define GPIO23_BASE UL(0xFFF0C000) +#define GPIO24_BASE UL(0xFFF0D000) +#define GPIO25_BASE UL(0xFFF0E000) +#define GPIO26_BASE UL(0xFFF0F000) +#define GPIO27_BASE UL(0xFFF10000) +#define GPIO28_BASE UL(0xFFF1D000) #define TZC_REG_BASE 0xE8A21000 #define TZC_STAT0_REG (TZC_REG_BASE + 0x800) diff --git a/plat/hisilicon/hikey960/platform.mk b/plat/hisilicon/hikey960/platform.mk index 6cb53c7b6..8ebabebc9 100644 --- a/plat/hisilicon/hikey960/platform.mk +++ b/plat/hisilicon/hikey960/platform.mk @@ -19,7 +19,7 @@ endif CRASH_CONSOLE_BASE := PL011_UART6_BASE COLD_BOOT_SINGLE_CPU := 1 -PLAT_PL061_MAX_GPIOS := 176 +PLAT_PL061_MAX_GPIOS := 232 PROGRAMMABLE_RESET_ADDRESS := 1 ENABLE_SVE_FOR_NS := 0 PLAT_PARTITION_BLOCK_SIZE := 4096 @@ -95,12 +95,15 @@ BL2_SOURCES += lib/optee/optee_utils.c endif BL31_SOURCES += drivers/arm/cci/cci.c \ + drivers/arm/pl061/pl061_gpio.c \ + drivers/gpio/gpio.c \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a72.S \ lib/cpus/aarch64/cortex_a73.S \ plat/common/plat_psci_common.c \ plat/hisilicon/hikey960/aarch64/hikey960_helpers.S \ plat/hisilicon/hikey960/hikey960_bl31_setup.c \ + plat/hisilicon/hikey960/hikey960_bl_common.c \ plat/hisilicon/hikey960/hikey960_pm.c \ plat/hisilicon/hikey960/hikey960_topology.c \ plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c \