feat(plat/marvell): introduce t9130_cex7_eval
This patch adds the necessary files to support the SolidRun CN913X CEx7 Evaluation Board. Because the DRAM connectivity and SerDes settings is shared with the CN913X DB - reuse relevant board-specific files. Change-Id: I75a4554a4373953ca3fdf3b04c4a29c2c4f8ea80 Signed-off-by: Marcin Wojtas <mw@semihalf.com>
This commit is contained in:
Marcin Wojtas
parent
0b702afc3a
commit
d01139f3b5
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@ -62,6 +62,7 @@ There are several build options:
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- a80x0_mcbin - MacchiatoBin
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- a80x0_puzzle - IEI Puzzle-M801
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- t9130 - CN913x
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- t9130_cex7_eval - CN913x CEx7 Evaluation Board
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- DEBUG
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@ -0,0 +1,224 @@
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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* Copyright (C) 2021 Semihalf.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <armada_common.h>
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#include <mvebu_def.h>
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/*
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* If bootrom is currently at BLE there's no need to include the memory
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* maps structure at this point
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*/
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#ifndef IMAGE_BLE
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/*****************************************************************************
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* AMB Configuration
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*****************************************************************************
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*/
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struct addr_map_win amb_memory_map_cp0[] = {
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/* CP0 SPI1 CS0 Direct Mode access */
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{0xef00, 0x1000000, AMB_SPI1_CS0_ID},
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};
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struct addr_map_win amb_memory_map_cp1[] = {
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/* CP1 SPI1 CS0 Direct Mode access */
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{0xe800, 0x1000000, AMB_SPI1_CS0_ID},
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};
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int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size,
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uintptr_t base)
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{
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switch (base) {
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case MVEBU_CP_REGS_BASE(0):
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*win = amb_memory_map_cp0;
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*size = ARRAY_SIZE(amb_memory_map_cp0);
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return 0;
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case MVEBU_CP_REGS_BASE(1):
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*win = amb_memory_map_cp1;
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*size = ARRAY_SIZE(amb_memory_map_cp1);
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return 0;
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case MVEBU_CP_REGS_BASE(2):
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default:
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*size = 0;
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*win = 0;
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return 1;
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}
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}
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#endif
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/*****************************************************************************
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* IO WIN Configuration
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*****************************************************************************
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*/
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struct addr_map_win io_win_memory_map[] = {
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#if (CP_COUNT > 1)
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/* SB (MCi0) internal regs */
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{0x00000000f4000000, 0x2000000, MCI_0_TID},
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/* SB (MCi0) PCIe0-2 on CP1 */
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{0x00000000e2000000, 0x7000000, MCI_0_TID},
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/*
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* Due to lack of sufficient number of IO windows registers,
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* below CP1 PCIE configuration must be performed in the
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* later firmware stages. It should replace the MCI 0 indirect
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* window, which becomes no longer needed.
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*/
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/* {0x0000000890000000, 0x30000000, MCI_0_TID}, */
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#if (CP_COUNT > 2)
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/* SB (MCi1) internal regs */
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{0x00000000f6000000, 0x2000000, MCI_1_TID},
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/* SB (MCi1) PCIe0-2 on CP2 */
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{0x00000000e9000000, 0x6000000, MCI_1_TID},
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/*
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* Due to lack of sufficient number of IO windows registers,
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* below CP2 PCIE configuration must be performed in the
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* later firmware stages. It should replace the MCI 1 indirect
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* window, which becomes no longer needed.
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*/
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/* {0x00000008c0000000, 0x30000000, MCI_1_TID}, */
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#endif
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#endif
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#ifndef IMAGE_BLE
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/* MCI 0 indirect window */
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{MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID},
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/* MCI 1 indirect window */
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{MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID},
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#endif
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};
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/* Global Control Register - window default target */
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uint32_t marvell_get_io_win_gcr_target(int ap_index)
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{
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/*
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* PIDI == iMCIP AP to SB internal MoChi connection.
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* In other words CP0
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*/
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return PIDI_TID;
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}
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int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win,
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uint32_t *size)
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{
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*win = io_win_memory_map;
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if (*win == NULL)
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*size = 0;
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else
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*size = ARRAY_SIZE(io_win_memory_map);
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return 0;
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}
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#ifndef IMAGE_BLE
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/*****************************************************************************
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* IOB Configuration
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*****************************************************************************
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*/
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struct addr_map_win iob_memory_map_cp0[] = {
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/* SPI1_CS0 (RUNIT) window */
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{0x00000000ef000000, 0x1000000, RUNIT_TID},
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/* PEX2_X1 window */
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{0x00000000e1000000, 0x1000000, PEX2_TID},
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/* PEX1_X1 window */
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{0x00000000e0000000, 0x1000000, PEX1_TID},
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/* PEX0_X4 window */
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{0x00000000c0000000, 0x20000000, PEX0_TID},
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{0x0000000800000000, 0x90000000, PEX0_TID},
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};
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struct addr_map_win iob_memory_map_cp1[] = {
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/* SPI1_CS0 (RUNIT) window */
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{0x00000000e8000000, 0x1000000, RUNIT_TID},
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/* PEX2_X1 window */
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{0x00000000e6000000, 0x2000000, PEX2_TID},
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{0x00000008b0000000, 0x10000000, PEX2_TID},
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/* PEX1_X1 window */
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{0x00000000e4000000, 0x2000000, PEX1_TID},
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{0x00000008a0000000, 0x10000000, PEX1_TID},
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/* PEX0_X2 window */
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{0x00000000e2000000, 0x2000000, PEX0_TID},
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{0x0000000890000000, 0x10000000, PEX0_TID},
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};
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struct addr_map_win iob_memory_map_cp2[] = {
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/* PEX2_X1 window */
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{0x00000000ed000000, 0x2000000, PEX2_TID},
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{0x00000008e0000000, 0x10000000, PEX2_TID},
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/* PEX1_X1 window */
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{0x00000000eb000000, 0x2000000, PEX1_TID},
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{0x00000008d0000000, 0x10000000, PEX1_TID},
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/* PEX0_X1 window */
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{0x00000000e9000000, 0x2000000, PEX0_TID},
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{0x00000008c0000000, 0x10000000, PEX0_TID},
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};
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int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size,
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uintptr_t base)
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{
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switch (base) {
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case MVEBU_CP_REGS_BASE(0):
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*win = iob_memory_map_cp0;
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*size = ARRAY_SIZE(iob_memory_map_cp0);
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return 0;
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case MVEBU_CP_REGS_BASE(1):
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*win = iob_memory_map_cp1;
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*size = ARRAY_SIZE(iob_memory_map_cp1);
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return 0;
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case MVEBU_CP_REGS_BASE(2):
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*win = iob_memory_map_cp2;
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*size = ARRAY_SIZE(iob_memory_map_cp2);
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return 0;
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default:
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*size = 0;
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*win = 0;
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return 1;
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}
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}
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#endif
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/*****************************************************************************
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* CCU Configuration
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*****************************************************************************
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*/
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struct addr_map_win ccu_memory_map[] = { /* IO window */
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#ifdef IMAGE_BLE
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{0x00000000f2000000, 0x6000000, IO_0_TID}, /* IO window */
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#else
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#if LLC_SRAM
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{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
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#endif
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{0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */
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{0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
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{0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
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{0x0000002000000000, 0x70e000000, IO_0_TID}, /* IO for CV-OS */
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#endif
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};
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uint32_t marvell_get_ccu_gcr_target(int ap)
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{
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return DRAM_0_TID;
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}
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int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win,
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uint32_t *size)
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{
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*win = ccu_memory_map;
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*size = ARRAY_SIZE(ccu_memory_map);
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return 0;
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}
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#ifdef IMAGE_BLE
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/*****************************************************************************
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* SKIP IMAGE Configuration
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*****************************************************************************
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*/
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void *plat_get_skip_image_data(void)
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{
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/* No recovery button on CN-9130 board? */
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return NULL;
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}
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#endif
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@ -0,0 +1,33 @@
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#
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# Copyright (C) 2018 Marvell International Ltd.
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# Copyright (C) 2021 Semihalf.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# https://spdx.org/licenses
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#
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PCI_EP_SUPPORT := 0
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CP_NUM := 1
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$(eval $(call add_define,CP_NUM))
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DOIMAGE_SEC := tools/doimage/secure/sec_img_7K.cfg
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MARVELL_MOCHI_DRV := drivers/marvell/mochi/ap807_setup.c
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BOARD_DIR := $(shell dirname $(lastword $(MAKEFILE_LIST)))
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#
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# CN913X CEx7 Evaluation Board shares the DRAM connectivity
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# and SerDes settings with the CN913X DB - reuse relevant
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# board-specific files.
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#
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T9130_DIR := $(BOARD_DIR)/../t9130
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PLAT_INCLUDES := -I$(T9130_DIR) \
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-I$(T9130_DIR)/board
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BLE_PORTING_SOURCES := $(T9130_DIR)/board/dram_port.c \
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$(BOARD_DIR)/board/marvell_plat_config.c
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include plat/marvell/armada/a8k/common/a8k_common.mk
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include plat/marvell/armada/common/marvell_common.mk
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