From d09adcbaf2c443ef7dde66fda5e9c568ff02e7a1 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Wed, 23 Oct 2019 18:34:14 +0800 Subject: [PATCH] intel: Refactor common platform code [3/5] Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by: Hadi Asyrafi Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716 --- plat/intel/soc/agilex/bl2_plat_setup.c | 2 +- plat/intel/soc/agilex/platform.mk | 4 +- plat/intel/soc/agilex/socfpga_psci.c | 2 +- plat/intel/soc/agilex/socfpga_sip_svc.c | 2 +- .../include/socfpga_mailbox.h} | 6 +- .../soc/socfpga_mailbox.c} | 2 +- plat/intel/soc/stratix10/bl2_plat_setup.c | 2 +- plat/intel/soc/stratix10/bl31_plat_setup.c | 1 - .../intel/soc/stratix10/include/s10_mailbox.h | 125 -------- plat/intel/soc/stratix10/plat_psci.c | 2 +- plat/intel/soc/stratix10/plat_sip_svc.c | 2 +- plat/intel/soc/stratix10/platform.mk | 4 +- plat/intel/soc/stratix10/soc/s10_mailbox.c | 275 ------------------ 13 files changed, 14 insertions(+), 415 deletions(-) rename plat/intel/soc/{agilex/include/agilex_mailbox.h => common/include/socfpga_mailbox.h} (98%) rename plat/intel/soc/{agilex/soc/agilex_mailbox.c => common/soc/socfpga_mailbox.c} (99%) delete mode 100644 plat/intel/soc/stratix10/include/s10_mailbox.h delete mode 100644 plat/intel/soc/stratix10/soc/s10_mailbox.c diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c index d65049d1b..ece7b9c70 100644 --- a/plat/intel/soc/agilex/bl2_plat_setup.c +++ b/plat/intel/soc/agilex/bl2_plat_setup.c @@ -17,7 +17,6 @@ #include #include "agilex_clock_manager.h" -#include "agilex_mailbox.h" #include "agilex_memory_controller.h" #include "agilex_pinmux.h" #include "agilex_reset_manager.h" @@ -26,6 +25,7 @@ #include "ccu/ncore_ccu.h" #include "qspi/cadence_qspi.h" #include "socfpga_handoff.h" +#include "socfpga_mailbox.h" #include "socfpga_private.h" #include "wdt/watchdog.h" diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index b523d9ccf..bf8fc36b2 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -47,7 +47,7 @@ BL2_SOURCES += \ plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/agilex/soc/agilex_system_manager.c \ - plat/intel/soc/agilex/soc/agilex_mailbox.c \ + plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c \ plat/intel/soc/common/drivers/ccu/ncore_ccu.c @@ -65,7 +65,7 @@ BL31_SOURCES += \ plat/intel/soc/agilex/soc/agilex_reset_manager.c \ plat/intel/soc/agilex/soc/agilex_pinmux.c \ plat/intel/soc/agilex/soc/agilex_clock_manager.c \ - plat/intel/soc/agilex/soc/agilex_mailbox.c + plat/intel/soc/common/soc/socfpga_mailbox.c PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 diff --git a/plat/intel/soc/agilex/socfpga_psci.c b/plat/intel/soc/agilex/socfpga_psci.c index 12060ef08..4b29159bd 100644 --- a/plat/intel/soc/agilex/socfpga_psci.c +++ b/plat/intel/soc/agilex/socfpga_psci.c @@ -12,7 +12,7 @@ #include #include "agilex_reset_manager.h" -#include "agilex_mailbox.h" +#include "socfpga_mailbox.h" #define AGX_RSTMGR_OFST 0xffd11000 #define AGX_RSTMGR_MPUMODRST_OFST 0x20 diff --git a/plat/intel/soc/agilex/socfpga_sip_svc.c b/plat/intel/soc/agilex/socfpga_sip_svc.c index 6a1c957c3..16e3c0393 100644 --- a/plat/intel/soc/agilex/socfpga_sip_svc.c +++ b/plat/intel/soc/agilex/socfpga_sip_svc.c @@ -9,7 +9,7 @@ #include #include -#include "agilex_mailbox.h" +#include "socfpga_mailbox.h" /* Number of SiP Calls implemented */ #define SIP_NUM_CALLS 0x3 diff --git a/plat/intel/soc/agilex/include/agilex_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h similarity index 98% rename from plat/intel/soc/agilex/include/agilex_mailbox.h rename to plat/intel/soc/common/include/socfpga_mailbox.h index cd8be2894..db4c84104 100644 --- a/plat/intel/soc/agilex/include/agilex_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef AGX_MBOX_H -#define AGX_MBOX_H +#ifndef SOCFPGA_MBOX_H +#define SOCFPGA_MBOX_H #include @@ -124,4 +124,4 @@ int mailbox_read_response(int job_id, uint32_t *response); int mailbox_get_qspi_clock(void); void mailbox_reset_cold(void); -#endif +#endif /* SOCFPGA_MBOX_H */ diff --git a/plat/intel/soc/agilex/soc/agilex_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c similarity index 99% rename from plat/intel/soc/agilex/soc/agilex_mailbox.c rename to plat/intel/soc/common/soc/socfpga_mailbox.c index ebfea6148..27838bfe7 100644 --- a/plat/intel/soc/agilex/soc/agilex_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -7,7 +7,7 @@ #include #include -#include "agilex_mailbox.h" +#include "socfpga_mailbox.h" static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, int len) diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index 1cb9c250c..7376b4143 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -27,9 +27,9 @@ #include "s10_reset_manager.h" #include "s10_clock_manager.h" #include "s10_pinmux.h" -#include "include/s10_mailbox.h" #include "qspi/cadence_qspi.h" #include "socfpga_handoff.h" +#include "socfpga_mailbox.h" #include "socfpga_private.h" #include "wdt/watchdog.h" diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index 0a7f21873..9887cb1d5 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/plat/intel/soc/stratix10/include/s10_mailbox.h b/plat/intel/soc/stratix10/include/s10_mailbox.h deleted file mode 100644 index 554c26566..000000000 --- a/plat/intel/soc/stratix10/include/s10_mailbox.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __S10_MBOX__ -#define __S10_MBOX__ - -#define MBOX_OFFSET 0xffa30000 - -#define MBOX_ATF_CLIENT_ID 0x1 -#define MBOX_JOB_ID 0x1 - -/* Mailbox interrupt flags and masks */ -#define MBOX_INT_FLAG_COE 0x1 -#define MBOX_INT_FLAG_RIE 0x2 -#define MBOX_INT_FLAG_UAE 0x100 -#define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3) -#define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<4))) - -/* Mailbox response and status */ -#define MBOX_RESP_BUFFER_SIZE 16 -#define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x00000fff) -#define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12) -#define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28) -#define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24) -#define MBOX_STATUS_UA_MASK (1<<8) - -/* Mailbox command and response */ -#define MBOX_CMD_FREE_OFFSET 0x14 -#define MBOX_CMD_BUFFER_SIZE 32 -#define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28) -#define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24) -#define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12) -#define MBOX_INDIRECT (1 << 11) -#define MBOX_INSUFFICIENT_BUFFER -2 -#define MBOX_CIN 0x00 -#define MBOX_ROUT 0x04 -#define MBOX_URG 0x08 -#define MBOX_INT 0x0C -#define MBOX_COUT 0x20 -#define MBOX_RIN 0x24 -#define MBOX_STATUS 0x2C -#define MBOX_CMD_BUFFER 0x40 -#define MBOX_RESP_BUFFER 0xC0 - -#define MBOX_RESP_BUFFER_SIZE 16 -#define MBOX_RESP_OK 0 -#define MBOX_RESP_INVALID_CMD 1 -#define MBOX_RESP_UNKNOWN_BR 2 -#define MBOX_RESP_UNKNOWN 3 -#define MBOX_RESP_NOT_CONFIGURED 256 - -/* Mailbox SDM doorbell */ -#define MBOX_DOORBELL_TO_SDM 0x400 -#define MBOX_DOORBELL_FROM_SDM 0x480 - -/* Mailbox QSPI commands */ -#define MBOX_CMD_RESTART 2 -#define MBOX_CMD_QSPI_OPEN 50 -#define MBOX_CMD_QSPI_CLOSE 51 -#define MBOX_CMD_QSPI_DIRECT 59 -#define MBOX_CMD_GET_IDCODE 16 -#define MBOX_CMD_QSPI_SET_CS 52 - -/* Mailbox REBOOT commands */ -#define MBOX_CMD_REBOOT_HPS 71 - -/* Generic error handling */ -#define MBOX_TIMEOUT -2047 -#define MBOX_NO_RESPONSE -2 -#define MBOX_WRONG_ID -3 - -/* Mailbox status */ -#define RECONFIG_STATUS_STATE 0 -#define RECONFIG_STATUS_PIN_STATUS 2 -#define RECONFIG_STATUS_SOFTFUNC_STATUS 3 -#define PIN_STATUS_NSTATUS (1U << 31) -#define SOFTFUNC_STATUS_SEU_ERROR (1 << 3) -#define SOFTFUNC_STATUS_INIT_DONE (1 << 1) -#define SOFTFUNC_STATUS_CONF_DONE (1 << 0) -#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 - -/* SMC function IDs for SiP Service queries */ -#define SIP_SVC_CALL_COUNT 0x8200ff00 -#define SIP_SVC_UID 0x8200ff01 -#define SIP_SVC_VERSION 0x8200ff03 - -/* SiP Service Calls version numbers */ -#define SIP_SVC_VERSION_MAJOR 0 -#define SIP_SVC_VERSION_MINOR 1 - -/* Mailbox reconfiguration commands */ -#define MBOX_RECONFIG 6 -#define MBOX_RECONFIG_DATA 8 -#define MBOX_RECONFIG_STATUS 9 - -/* Sip get memory */ -#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001 -#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005 -#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004 -#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002 -#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003 -#define INTEL_SIP_SMC_STATUS_OK 0 -#define INTEL_SIP_SMC_STATUS_ERROR 0x4 -#define INTEL_SIP_SMC_STATUS_BUSY 0x1 -#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 -#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x1000 -#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 16777216 - -void mailbox_set_int(int interrupt_input); -int mailbox_init(void); -void mailbox_set_qspi_close(void); -void mailbox_set_qspi_open(void); -void mailbox_set_qspi_direct(void); -int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent, uint32_t *response); -void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent); -int mailbox_read_response(int job_id, uint32_t *response); -int mailbox_get_qspi_clock(void); -void mailbox_reset_cold(void); - -#endif diff --git a/plat/intel/soc/stratix10/plat_psci.c b/plat/intel/soc/stratix10/plat_psci.c index f4a970e75..73389c95d 100644 --- a/plat/intel/soc/stratix10/plat_psci.c +++ b/plat/intel/soc/stratix10/plat_psci.c @@ -16,7 +16,7 @@ #include "platform_def.h" #include "s10_reset_manager.h" -#include "s10_mailbox.h" +#include "socfpga_mailbox.h" #define S10_RSTMGR_OFST 0xffd11000 #define S10_RSTMGR_MPUMODRST_OFST 0x20 diff --git a/plat/intel/soc/stratix10/plat_sip_svc.c b/plat/intel/soc/stratix10/plat_sip_svc.c index 2c2332ba9..23a009d12 100644 --- a/plat/intel/soc/stratix10/plat_sip_svc.c +++ b/plat/intel/soc/stratix10/plat_sip_svc.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include /* Number of SiP Calls implemented */ diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index d1ff07761..2ed1cb442 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -46,7 +46,7 @@ BL2_SOURCES += \ plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/stratix10/soc/s10_system_manager.c \ common/desc_image_load.c \ - plat/intel/soc/stratix10/soc/s10_mailbox.c \ + plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c @@ -63,7 +63,7 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ plat/intel/soc/stratix10/soc/s10_reset_manager.c\ plat/intel/soc/stratix10/soc/s10_pinmux.c \ plat/intel/soc/stratix10/soc/s10_clock_manager.c\ - plat/intel/soc/stratix10/soc/s10_mailbox.c + plat/intel/soc/common/soc/socfpga_mailbox.c PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 diff --git a/plat/intel/soc/stratix10/soc/s10_mailbox.c b/plat/intel/soc/stratix10/soc/s10_mailbox.c deleted file mode 100644 index 00a07f33a..000000000 --- a/plat/intel/soc/stratix10/soc/s10_mailbox.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include "s10_mailbox.h" - -static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, - int len) -{ - uint32_t cmd_free_offset; - int i; - - cmd_free_offset = mmio_read_32(MBOX_OFFSET + MBOX_CIN); - - if (cmd_free_offset >= MBOX_CMD_BUFFER_SIZE) { - INFO("Insufficient buffer in mailbox\n"); - return MBOX_INSUFFICIENT_BUFFER; - } - - - mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + (cmd_free_offset++ * 4), - header_cmd); - - - for (i = 0; i < len; i++) { - cmd_free_offset %= MBOX_CMD_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + - (cmd_free_offset++ * 4), args[i]); - } - - cmd_free_offset %= MBOX_CMD_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_CIN, cmd_free_offset); - - return 0; -} - -int mailbox_read_response(int job_id, uint32_t *response) -{ - int rin = 0; - int rout = 0; - int response_length = 0; - int resp = 0; - int total_resp_len = 0; - int timeout = 100000; - - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); - - while (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) { - if (timeout-- < 0) - return MBOX_NO_RESPONSE; - } - - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); - - rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); - rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); - - while (rout != rin) { - resp = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + ((rout++)*4)); - - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - - if (MBOX_RESP_CLIENT_ID(resp) != MBOX_ATF_CLIENT_ID || - MBOX_RESP_JOB_ID(resp) != job_id) { - return MBOX_WRONG_ID; - } - - if (MBOX_RESP_ERR(resp) > 0) { - INFO("Error in response: %x\n", resp); - return -resp; - } - response_length = MBOX_RESP_LEN(resp); - - while (response_length) { - - response_length--; - resp = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + - (rout)*4); - if (response) { - *(response + total_resp_len) = resp; - total_resp_len++; - } - rout++; - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - } - return total_resp_len; - } - - return MBOX_NO_RESPONSE; -} - - -int mailbox_poll_response(int job_id, int urgent, uint32_t *response) -{ - int timeout = 80000; - int rin = 0; - int rout = 0; - int response_length = 0; - int resp = 0; - int total_resp_len = 0; - - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); - - while (1) { - while (timeout > 0 && - mmio_read_32(MBOX_OFFSET + - MBOX_DOORBELL_FROM_SDM) != 1) { - timeout--; - } - - if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) { - INFO("Timed out waiting for SDM"); - return MBOX_TIMEOUT; - } - - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); - - if (urgent & 1) { - if ((mmio_read_32(MBOX_OFFSET + MBOX_STATUS) & - MBOX_STATUS_UA_MASK) ^ - (urgent & MBOX_STATUS_UA_MASK)) { - mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); - return 0; - } - - mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); - INFO("Error: Mailbox did not get UA"); - return -1; - } - - rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); - rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); - - while (rout != rin) { - resp = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + ((rout++)*4)); - - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - - if (MBOX_RESP_CLIENT_ID(resp) != MBOX_ATF_CLIENT_ID || - MBOX_RESP_JOB_ID(resp) != job_id) - continue; - - if (MBOX_RESP_ERR(resp) > 0) { - INFO("Error in response: %x\n", resp); - return -MBOX_RESP_ERR(resp); - } - response_length = MBOX_RESP_LEN(resp); - - while (response_length) { - - response_length--; - resp = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + - (rout)*4); - if (response) { - *(response + total_resp_len) = resp; - total_resp_len++; - } - rout++; - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - } - return total_resp_len; - } - } -} - -void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent) -{ - if (urgent) - mmio_write_32(MBOX_OFFSET + MBOX_URG, 1); - - fill_mailbox_circular_buffer(MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) | - MBOX_JOB_ID_CMD(job_id) | - MBOX_CMD_LEN_CMD(len) | - MBOX_INDIRECT | - cmd, args, len); -} - -int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent, uint32_t *response) -{ - int status; - - if (urgent) { - urgent |= mmio_read_32(MBOX_OFFSET + MBOX_STATUS) & - MBOX_STATUS_UA_MASK; - mmio_write_32(MBOX_OFFSET + MBOX_URG, 1); - } - - status = fill_mailbox_circular_buffer( - MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) | - MBOX_JOB_ID_CMD(job_id) | - cmd, args, len); - - if (status) - return status; - - return mailbox_poll_response(job_id, urgent, response); -} - -void mailbox_set_int(int interrupt) -{ - - mmio_write_32(MBOX_OFFSET+MBOX_INT, MBOX_COE_BIT(interrupt) | - MBOX_UAE_BIT(interrupt)); -} - - -void mailbox_set_qspi_open(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, 0, 0, 0, 0); -} - -void mailbox_set_qspi_direct(void) -{ - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, 0); -} - -void mailbox_set_qspi_close(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, 0, 0, 0, 0); -} - -int mailbox_get_qspi_clock(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, 0); -} - -void mailbox_qspi_set_cs(int device_select) -{ - uint32_t cs_setting = device_select; - - /* QSPI device select settings at 31:28 */ - cs_setting = (cs_setting << 28); - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_SET_CS, &cs_setting, - 1, 0, 0); -} - -void mailbox_reset_cold(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, 0, 0, 0, 0); -} - -int mailbox_init(void) -{ - int status = 0; - - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - status = mailbox_send_cmd(0, MBOX_CMD_RESTART, 0, 0, 1, 0); - - if (status) - return status; - - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - - return 0; -} -