Tegra194: toggle SE clock during context save/restore
This patch adds support to toggle SE clock, using the bpmp_ipc interface, to enable SE context save/restore. The SE sequence mostly gets called during System Suspend/Resume. Change-Id: I9cee12a9e14861d5e3c8c4f18b4d7f898b6ebfa7 Signed-off-by: steven kao <skao@nvidia.com>
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@ -151,6 +151,14 @@
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#define TEGRA_RNG1_BASE U(0x03AE0000)
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#define RNG1_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0)
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/*******************************************************************************
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* Tegra HSP doorbell #0 constants
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******************************************************************************/
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#define TEGRA_HSP_DBELL_BASE U(0x03C90000)
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#define HSP_DBELL_1_ENABLE U(0x104)
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#define HSP_DBELL_3_TRIGGER U(0x300)
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#define HSP_DBELL_3_ENABLE U(0x304)
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/*******************************************************************************
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* Tegra hardware synchronization primitives for the SPE engine
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******************************************************************************/
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@ -206,6 +214,13 @@
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#define TEGRA_TZRAM_BASE U(0x40000000)
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#define TEGRA_TZRAM_SIZE U(0x40000)
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/*******************************************************************************
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* Tegra CCPLEX-BPMP IPC constants
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******************************************************************************/
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#define TEGRA_BPMP_IPC_TX_PHYS_BASE U(0x4004C000)
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#define TEGRA_BPMP_IPC_RX_PHYS_BASE U(0x4004D000)
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#define TEGRA_BPMP_IPC_CH_MAP_SIZE U(0x1000) /* 4KB */
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/*******************************************************************************
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* Tegra Clock and Reset Controller constants
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******************************************************************************/
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -10,6 +10,7 @@
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#include <stdbool.h>
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#include <arch_helpers.h>
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#include <bpmp_ipc.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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@ -181,6 +182,12 @@ int32_t tegra_se_suspend(void)
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{
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int32_t ret = 0;
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/* initialise communication channel with BPMP */
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assert(tegra_bpmp_ipc_init() == 0);
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/* Enable SE clock before SE context save */
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tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
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/* save SE registers */
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se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT);
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se_regs[1] = mmio_read_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL);
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@ -193,6 +200,9 @@ int32_t tegra_se_suspend(void)
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ERROR("%s: context save failed (%d)\n", __func__, ret);
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}
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/* Disable SE clock after SE context save */
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tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
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return ret;
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}
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@ -201,6 +211,12 @@ int32_t tegra_se_suspend(void)
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*/
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void tegra_se_resume(void)
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{
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/* initialise communication channel with BPMP */
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assert(tegra_bpmp_ipc_init() == 0);
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/* Enable SE clock before SE context restore */
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tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
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/*
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* When TZ takes over after System Resume, TZ should first reconfigure
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* SE_MUTEX_WATCHDOG_NS_LIMIT, PKA1_MUTEX_WATCHDOG_NS_LIMIT,
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@ -211,4 +227,7 @@ void tegra_se_resume(void)
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mmio_write_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL, se_regs[1]);
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mmio_write_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[2]);
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mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]);
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/* Disable SE clock after SE context restore */
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tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
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}
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@ -86,6 +86,8 @@ static const mmap_region_t tegra_mmap[] = {
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x10000U, /* 64KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */
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@ -94,6 +96,8 @@ static const mmap_region_t tegra_mmap[] = {
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MAP_REGION_FLAT(TEGRA_AON_HSP_SM_6_7_BASE, 0x10000U, /* 64KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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#endif
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MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, 0x10000U, /* 64KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
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MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
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@ -38,6 +38,8 @@ PLAT_INCLUDES += -I${SOC_DIR}/drivers/include
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BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
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lib/cpus/aarch64/denver.S \
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${COMMON_DIR}/drivers/bpmp_ipc/intf.c \
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${COMMON_DIR}/drivers/bpmp_ipc/ivc.c \
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${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \
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${COMMON_DIR}/drivers/smmu/smmu.c \
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${SOC_DIR}/drivers/mce/mce.c \
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