Tegra194: remove L2 ECC parity protection setting
This patch removes the code to enable L2 ECC parity protection bit, as Tegra194 does not have any Cortex-A57 CPUs. Change-Id: I4b56595fea2652e8bb8ab4a7ae7567278ecff9af Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
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@ -25,9 +25,6 @@
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#include <tegra_private.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1)
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extern uint64_t tegra_enable_l2_ecc_parity_prot;
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/*******************************************************************************
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* The Tegra power domain tree has a single system level power domain i.e. a
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* single root node. The first entry in the power domain descriptor specifies
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@ -145,49 +142,15 @@ uint32_t plat_get_console_from_id(int id)
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return tegra186_uart_addresses[id];
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}
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/* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */
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#define TEGRA186_VER_A02P 0x1201
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/*******************************************************************************
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* Handler for early platform setup
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******************************************************************************/
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void plat_early_platform_setup(void)
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{
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int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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uint32_t chip_subrev, val;
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/* sanity check MCE firmware compatibility */
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mce_verify_firmware_version();
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/*
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* Enable ECC and Parity Protection for Cortex-A57 CPUs
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* for Tegra A02p SKUs
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*/
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if (impl != DENVER_IMPL) {
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/* get the major, minor and sub-version values */
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chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) &
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SUBREVISION_MASK;
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/* prepare chip version number */
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val = (tegra_get_chipid_major() << 12) |
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(tegra_get_chipid_minor() << 8) |
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chip_subrev;
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/* enable L2 ECC for Tegra186 A02P and beyond */
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if (val >= TEGRA186_VER_A02P) {
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val = read_l2ctlr_el1();
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val |= L2_ECC_PARITY_PROTECTION_BIT;
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write_l2ctlr_el1(val);
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/*
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* Set the flag to enable ECC/Parity Protection
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* when we exit System Suspend or Cluster Powerdn
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*/
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tegra_enable_l2_ecc_parity_prot = 1;
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}
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}
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}
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/* Secure IRQs for Tegra186 */
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