commit
d1d92a23ec
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@ -199,9 +199,6 @@ void bl2_main(void)
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/* Perform remaining generic architectural setup in S-EL1 */
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bl2_arch_setup();
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/* Perform platform setup in BL2 */
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bl2_platform_setup();
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/*
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* Load the subsequent bootloader images
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*/
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@ -211,6 +208,9 @@ void bl2_main(void)
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panic();
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}
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/* Perform platform setup in BL2 after loading BL3-0 */
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bl2_platform_setup();
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/*
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* Get a pointer to the memory the platform has set aside to pass
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* information to BL3-1.
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@ -1306,6 +1306,8 @@ other boot loader images in Trusted SRAM.
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#### Memory layout on Juno ARM development platform
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**TSP in Trusted SRAM (default option):**
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Flash0
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0x0C000000 +----------+
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: :
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@ -1329,6 +1331,40 @@ other boot loader images in Trusted SRAM.
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| MHU |
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0x04000000 +----------+
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**TSP in the secure region of DRAM:**
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DRAM
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0xFFE00000 +----------+
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| BL3-2 |
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0xFF000000 |----------|
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| |
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: :
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| |
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0x80000000 +----------+
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Flash0
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0x0C000000 +----------+
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: :
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0x0BED0000 |----------|
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| BL1 (ro) |
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0x0BEC0000 |----------|
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: :
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| Bypass |
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0x08000000 +----------+
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Trusted SRAM
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0x04040000 +----------+
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| BL2 | BL3-1 is loaded
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0x04033000 |----------| after BL3-0 has
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| | been sent to SCP
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0x04023000 |----------| ------------------
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| BL3-0 | <<<<<<<<<<<<< | BL3-1 |
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0x04009000 |----------| ------------------
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| BL1 (rw) |
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0x04001000 |----------|
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| MHU |
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0x04000000 +----------+
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The Message Handling Unit (MHU) page contains the entrypoint mailboxes and a
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shared memory area. This shared memory is used as a communication channel
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between the AP and the SCP.
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@ -256,6 +256,12 @@ performed.
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For a better understanding of FVP options, the FVP memory map is explained in
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the [Firmware Design].
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#### Juno specific build options
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* `PLAT_TSP_LOCATION`: location of the TSP binary. Options:
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- `tsram` : Trusted SRAM (default option)
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- `dram` : Secure region in DRAM (set by the TrustZone controller)
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### Creating a Firmware Image Package
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FIPs are automatically created as part of the build instructions described in
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@ -243,7 +243,7 @@ void tzc_configure_region(uint32_t filters,
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/* Assign the region to a filter and set secure attributes */
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tzc_write_region_attributes(tzc.base, region,
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(sec_attr << REGION_ATTRIBUTES_SEC_SHIFT) | filters);
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(sec_attr << REG_ATTR_SEC_SHIFT) | filters);
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/*
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* Specify which non-secure devices have permission to access this
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@ -126,9 +126,12 @@
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#define FAIL_ID_ID_SHIFT 0
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/* Used along with 'tzc_region_attributes_t' below */
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#define REGION_ATTRIBUTES_SEC_SHIFT 30
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#define REGION_ATTRIBUTES_F_EN_SHIFT 0
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#define REGION_ATTRIBUTES_F_EN_MASK 0xf
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#define REG_ATTR_SEC_SHIFT 30
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#define REG_ATTR_F_EN_SHIFT 0
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#define REG_ATTR_F_EN_MASK 0xf
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#define REG_ATTR_FILTER_BIT(x) ((1 << x) << REG_ATTR_F_EN_SHIFT)
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#define REG_ATTR_FILTER_BIT_ALL (REG_ATTR_F_EN_MASK << \
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REG_ATTR_F_EN_SHIFT)
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#define REGION_ID_ACCESS_NSAID_WR_EN_SHIFT 16
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#define REGION_ID_ACCESS_NSAID_RD_EN_SHIFT 0
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@ -60,9 +60,14 @@
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DEVICE1_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_DRAM MAP_REGION_FLAT(DRAM_BASE, \
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DRAM_SIZE, \
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#define MAP_NS_DRAM MAP_REGION_FLAT(DRAM_NS_BASE, \
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DRAM_NS_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
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TSP_SEC_MEM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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/*
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* Table of regions for different BL stages to map using the MMU.
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* This doesn't include Trusted RAM as the 'mem_layout' argument passed to
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@ -85,7 +90,8 @@ static const mmap_region_t juno_mmap[] = {
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MAP_IOFPGA,
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MAP_DEVICE0,
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MAP_DEVICE1,
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MAP_DRAM,
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MAP_NS_DRAM,
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MAP_TSP_MEM,
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{0}
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};
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#endif
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@ -37,7 +37,6 @@
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#include <mmio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <tzc400.h>
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#include "../../bl1/bl1_private.h"
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#include "juno_def.h"
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#include "juno_private.h"
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@ -150,36 +149,6 @@ static void init_nic400(void)
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}
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static void init_tzc400(void)
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{
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/* Enable all filter units available */
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mmio_write_32(TZC400_BASE + GATE_KEEPER_OFF, 0x0000000f);
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/*
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* Secure read and write are enabled for region 0, and the background
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* region (region 0) is enabled for all four filter units
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*/
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mmio_write_32(TZC400_BASE + REGION_ATTRIBUTES_OFF, 0xc0000000);
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/*
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* Enable Non-secure read/write accesses for the Soc Devices from the
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* Non-Secure World
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*/
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mmio_write_32(TZC400_BASE + REGION_ID_ACCESS_OFF,
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_SCP) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)
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);
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}
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#define PCIE_SECURE_REG 0x3000
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#define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) /* REG and MEM access bits */
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@ -200,7 +169,6 @@ static void init_pcie(void)
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void bl1_platform_setup(void)
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{
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init_nic400();
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init_tzc400();
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init_pcie();
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/* Initialise the IO layer and register platform IO devices */
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@ -162,6 +162,9 @@ void bl2_early_platform_setup(meminfo_t *mem_layout)
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/* Setup the BL2 memory layout */
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bl2_tzram_layout = *mem_layout;
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/* Initialise the IO layer and register platform IO devices */
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io_setup();
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}
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/*******************************************************************************
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@ -171,8 +174,8 @@ void bl2_early_platform_setup(meminfo_t *mem_layout)
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******************************************************************************/
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void bl2_platform_setup(void)
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{
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/* Initialise the IO layer and register platform IO devices */
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io_setup();
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/* Initialize the secure environment */
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plat_security_setup();
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}
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/* Flush the TF params and the TF plat params */
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@ -309,8 +312,8 @@ void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
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******************************************************************************/
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void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
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{
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bl33_meminfo->total_base = DRAM_BASE;
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bl33_meminfo->total_size = DRAM_SIZE;
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bl33_meminfo->free_base = DRAM_BASE;
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bl33_meminfo->free_size = DRAM_SIZE;
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bl33_meminfo->total_base = DRAM_NS_BASE;
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bl33_meminfo->total_size = DRAM_NS_SIZE;
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bl33_meminfo->free_base = DRAM_NS_BASE;
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bl33_meminfo->free_size = DRAM_NS_SIZE;
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}
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@ -125,10 +125,20 @@
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/*******************************************************************************
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* BL3-2 specific defines.
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******************************************************************************/
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#define TSP_SEC_MEM_BASE TZRAM_BASE
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#define TSP_SEC_MEM_SIZE TZRAM_SIZE
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#define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1d000)
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#define BL32_LIMIT BL2_BASE
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#if (PLAT_TSP_LOCATION_ID == PLAT_TRUSTED_SRAM_ID)
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# define TSP_SEC_MEM_BASE TZRAM_BASE
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# define TSP_SEC_MEM_SIZE TZRAM_SIZE
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# define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1d000)
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# define BL32_LIMIT BL2_BASE
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#elif (PLAT_TSP_LOCATION_ID == PLAT_DRAM_ID)
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# define TSP_SEC_MEM_BASE DRAM_SEC_BASE
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# define TSP_SEC_MEM_SIZE (DRAM_SEC_SIZE - DRAM_SCP_SIZE)
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# define BL32_BASE DRAM_SEC_BASE
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# define BL32_LIMIT (DRAM_SEC_BASE + DRAM_SEC_SIZE - \
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DRAM_SCP_SIZE)
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#else
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# error "Unsupported PLAT_TSP_LOCATION_ID value"
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#endif
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/*******************************************************************************
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* Load address of BL3-3 in the Juno port
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@ -139,7 +149,15 @@
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define ADDR_SPACE_SIZE (1ull << 32)
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#define MAX_XLAT_TABLES 2
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#if IMAGE_BL1 || IMAGE_BL31
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# define MAX_XLAT_TABLES 2
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#endif
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#if IMAGE_BL2 || IMAGE_BL32
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# define MAX_XLAT_TABLES 3
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#endif
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#define MAX_MMAP_REGIONS 16
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/*******************************************************************************
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@ -37,6 +37,9 @@
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/*******************************************************************************
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* Juno memory map related constants
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******************************************************************************/
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#define PLAT_TRUSTED_SRAM_ID 0
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#define PLAT_DRAM_ID 1
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#define MHU_SECURE_BASE 0x04000000
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#define MHU_SECURE_SIZE 0x00001000
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@ -73,6 +76,26 @@
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#define DRAM_BASE 0x80000000
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#define DRAM_SIZE 0x80000000
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/*
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* DRAM at 0x8000_0000 is divided in two regions:
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* - Secure DRAM (default is the top 16MB except for the last 2MB, which are
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* used by the SCP for DDR retraining)
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* - Non-Secure DRAM (remaining DRAM starting at DRAM_BASE)
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*/
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#define DRAM_SCP_SIZE 0x00200000
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#define DRAM_SCP_BASE (DRAM_BASE + DRAM_SIZE - DRAM_SCP_SIZE)
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#define DRAM_SEC_SIZE 0x00E00000
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#define DRAM_SEC_BASE (DRAM_SCP_BASE - DRAM_SEC_SIZE)
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#define DRAM_NS_BASE DRAM_BASE
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#define DRAM_NS_SIZE (DRAM_SIZE - DRAM_SCP_SIZE - DRAM_SEC_SIZE)
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/* Second region of DRAM */
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#define DRAM2_BASE 0x880000000
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#define DRAM2_SIZE 0x180000000
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/* Memory mapped Generic timer interfaces */
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#define SYS_CNTCTL_BASE 0x2a430000
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#define SYS_CNTREAD_BASE 0x2a800000
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@ -108,6 +108,9 @@ int plat_get_image_source(const char *image_name,
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uintptr_t *dev_handle,
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uintptr_t *image_spec);
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/* Declarations for security.c */
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void plat_security_setup(void);
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/*
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* Before calling this function BL2 is loaded in memory and its entrypoint
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* is set by load_image. This is a placeholder for the platform to change
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@ -0,0 +1,104 @@
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/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <tzc400.h>
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#include "juno_def.h"
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/*******************************************************************************
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* Initialize the TrustZone Controller. Configure Region 0 with Secure RW access
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* and allow Non-Secure masters full access
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******************************************************************************/
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static void init_tzc400(void)
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{
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tzc_init(TZC400_BASE);
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/* Disable filters. */
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tzc_disable_filters();
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/* Region 1 set to cover Non-Secure DRAM at 0x8000_0000. Apply the
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* same configuration to all filters in the TZC. */
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tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 1,
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DRAM_NS_BASE, DRAM_NS_BASE + DRAM_NS_SIZE - 1,
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TZC_REGION_S_NONE,
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT));
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/* Region 2 set to cover Secure DRAM */
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tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 2,
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DRAM_SEC_BASE, DRAM_SEC_BASE + DRAM_SEC_SIZE - 1,
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TZC_REGION_S_RDWR,
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0);
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/* Region 3 set to cover DRAM used by SCP for DDR retraining */
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tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 3,
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DRAM_SCP_BASE, DRAM_SCP_BASE + DRAM_SCP_SIZE - 1,
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TZC_REGION_S_NONE,
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_SCP));
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/* Region 4 set to cover Non-Secure DRAM at 0x8_8000_0000 */
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tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 4,
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DRAM2_BASE, DRAM2_BASE + DRAM2_SIZE - 1,
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TZC_REGION_S_NONE,
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) |
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT));
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/* Raise an exception if a NS device tries to access secure memory */
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tzc_set_action(TZC_ACTION_ERR);
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/* Enable filters. */
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tzc_enable_filters();
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}
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/*******************************************************************************
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* Initialize the secure environment. At this moment only the TrustZone
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* Controller is initialized.
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******************************************************************************/
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void plat_security_setup(void)
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{
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/* Initialize the TrustZone Controller */
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init_tzc400();
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}
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@ -28,6 +28,23 @@
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# POSSIBILITY OF SUCH DAMAGE.
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#
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# On Juno, the Secure Payload can be loaded either in Trusted SRAM (default) or
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# Secure DRAM allocated by the TrustZone Controller.
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PLAT_TSP_LOCATION := tsram
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ifeq (${PLAT_TSP_LOCATION}, tsram)
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PLAT_TSP_LOCATION_ID := PLAT_TRUSTED_SRAM_ID
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else ifeq (${PLAT_TSP_LOCATION}, dram)
|
||||
PLAT_TSP_LOCATION_ID := PLAT_DRAM_ID
|
||||
else
|
||||
$(error "Unsupported PLAT_TSP_LOCATION value")
|
||||
endif
|
||||
|
||||
# Process flags
|
||||
$(eval $(call add_define,PLAT_TSP_LOCATION_ID))
|
||||
|
||||
|
||||
PLAT_INCLUDES := -Iplat/juno/include/
|
||||
|
||||
PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \
|
||||
|
@ -47,10 +64,12 @@ BL1_SOURCES += drivers/arm/cci400/cci400.c \
|
|||
plat/juno/aarch64/plat_helpers.S \
|
||||
plat/juno/aarch64/juno_common.c
|
||||
|
||||
BL2_SOURCES += lib/locks/bakery/bakery_lock.c \
|
||||
BL2_SOURCES += drivers/arm/tzc400/tzc400.c \
|
||||
lib/locks/bakery/bakery_lock.c \
|
||||
plat/common/aarch64/platform_up_stack.S \
|
||||
plat/juno/bl2_plat_setup.c \
|
||||
plat/juno/mhu.c \
|
||||
plat/juno/plat_security.c \
|
||||
plat/juno/aarch64/plat_helpers.S \
|
||||
plat/juno/aarch64/juno_common.c \
|
||||
plat/juno/scp_bootloader.c \
|
||||
|
|
Loading…
Reference in New Issue