Tegra: handlers for common and SoC-specific SiP calls
This patch implements a handler for common SiP calls. A weak implementation for the SoC-specific handler has been provided which can be overridden by SoCs to implement any custom SiP calls. Change-Id: I45122892a84ea35d7b44be0f35dc15f6bb95193e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -59,4 +59,5 @@ BL31_SOURCES += drivers/arm/gic/gic_v2.c \
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${COMMON_DIR}/tegra_delay_timer.c \
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${COMMON_DIR}/tegra_delay_timer.c \
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${COMMON_DIR}/tegra_gic.c \
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${COMMON_DIR}/tegra_gic.c \
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${COMMON_DIR}/tegra_pm.c \
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${COMMON_DIR}/tegra_pm.c \
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${COMMON_DIR}/tegra_sip_calls.c \
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${COMMON_DIR}/tegra_topology.c
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${COMMON_DIR}/tegra_topology.c
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@ -32,7 +32,6 @@
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#include <arch_helpers.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <bl_common.h>
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#include <context_mgmt.h>
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#include <debug.h>
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#include <debug.h>
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#include <errno.h>
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#include <errno.h>
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#include <memctrl.h>
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#include <memctrl.h>
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@ -40,14 +39,30 @@
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#include <tegra_private.h>
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#include <tegra_private.h>
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/*******************************************************************************
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/*******************************************************************************
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* Tegra210 SiP SMCs
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* Common Tegra SiP SMCs
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******************************************************************************/
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******************************************************************************/
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#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
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#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
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/*******************************************************************************
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* SoC specific SiP handler
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******************************************************************************/
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#pragma weak plat_sip_handler
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int plat_sip_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x2,
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uint64_t x3,
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uint64_t x4,
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void *cookie,
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void *handle,
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uint64_t flags)
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{
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return -ENOTSUP;
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}
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/*******************************************************************************
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/*******************************************************************************
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* This function is responsible for handling all SiP calls from the NS world
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* This function is responsible for handling all SiP calls from the NS world
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******************************************************************************/
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******************************************************************************/
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uint64_t tegra210_sip_handler(uint32_t smc_fid,
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uint64_t tegra_sip_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x1,
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uint64_t x2,
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uint64_t x2,
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uint64_t x3,
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uint64_t x3,
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@ -64,6 +79,11 @@ uint64_t tegra210_sip_handler(uint32_t smc_fid,
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if (!ns)
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if (!ns)
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SMC_RET1(handle, SMC_UNK);
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SMC_RET1(handle, SMC_UNK);
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/* Check if this is a SoC specific SiP */
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err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
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if (err == 0)
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SMC_RET1(handle, err);
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switch (smc_fid) {
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switch (smc_fid) {
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case TEGRA_SIP_NEW_VIDEOMEM_REGION:
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case TEGRA_SIP_NEW_VIDEOMEM_REGION:
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@ -104,11 +124,11 @@ uint64_t tegra210_sip_handler(uint32_t smc_fid,
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/* Define a runtime service descriptor for fast SMC calls */
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/* Define a runtime service descriptor for fast SMC calls */
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DECLARE_RT_SVC(
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DECLARE_RT_SVC(
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tegra210_sip_fast,
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tegra_sip_fast,
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OEN_SIP_START,
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OEN_SIP_START,
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OEN_SIP_END,
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OEN_SIP_END,
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SMC_TYPE_FAST,
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SMC_TYPE_FAST,
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NULL,
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NULL,
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tegra210_sip_handler
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tegra_sip_handler
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);
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);
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@ -35,8 +35,6 @@
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#include <context_mgmt.h>
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#include <context_mgmt.h>
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#include <debug.h>
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#include <debug.h>
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#include <errno.h>
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#include <errno.h>
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#include <memctrl.h>
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#include <runtime_svc.h>
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#include <tegra_private.h>
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#include <tegra_private.h>
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#define NS_SWITCH_AARCH32 1
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#define NS_SWITCH_AARCH32 1
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@ -45,7 +43,6 @@
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/*******************************************************************************
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/*******************************************************************************
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* Tegra132 SiP SMCs
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* Tegra132 SiP SMCs
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******************************************************************************/
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******************************************************************************/
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#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
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#define TEGRA_SIP_AARCH_SWITCH 0x82000004
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#define TEGRA_SIP_AARCH_SWITCH 0x82000004
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/*******************************************************************************
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/*******************************************************************************
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@ -56,55 +53,19 @@
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#define SPSR64 SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)
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#define SPSR64 SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)
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/*******************************************************************************
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/*******************************************************************************
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* This function is responsible for handling all SiP calls from the NS world
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* This function is responsible for handling all T132 SiP calls
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******************************************************************************/
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******************************************************************************/
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uint64_t tegra132_sip_handler(uint32_t smc_fid,
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int plat_sip_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x1,
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uint64_t x2,
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uint64_t x2,
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uint64_t x3,
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uint64_t x3,
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uint64_t x4,
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uint64_t x4,
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void *cookie,
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void *cookie,
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void *handle,
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void *handle,
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uint64_t flags)
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uint64_t flags)
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{
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{
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uint32_t ns;
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int err;
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/* Determine which security state this SMC originated from */
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ns = is_caller_non_secure(flags);
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if (!ns)
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SMC_RET1(handle, SMC_UNK);
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switch (smc_fid) {
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switch (smc_fid) {
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case TEGRA_SIP_NEW_VIDEOMEM_REGION:
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/* clean up the high bits */
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x1 = (uint32_t)x1;
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x2 = (uint32_t)x2;
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/*
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* Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
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* or falls outside of the valid DRAM range
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*/
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err = bl31_check_ns_address(x1, x2);
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if (err)
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SMC_RET1(handle, err);
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/*
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* Check if Video Memory is aligned to 1MB.
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*/
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if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) {
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ERROR("Unaligned Video Memory base address!\n");
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SMC_RET1(handle, -ENOTSUP);
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}
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/* new video memory carveout settings */
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tegra_memctrl_videomem_setup(x1, x2);
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SMC_RET1(handle, 0);
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break;
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case TEGRA_SIP_AARCH_SWITCH:
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case TEGRA_SIP_AARCH_SWITCH:
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/* clean up the high bits */
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/* clean up the high bits */
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@ -113,7 +74,7 @@ uint64_t tegra132_sip_handler(uint32_t smc_fid,
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if (!x1 || x2 > NS_SWITCH_AARCH32) {
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if (!x1 || x2 > NS_SWITCH_AARCH32) {
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ERROR("%s: invalid parameters\n", __func__);
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ERROR("%s: invalid parameters\n", __func__);
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SMC_RET1(handle, SMC_UNK);
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return -EINVAL;
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}
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}
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/* x1 = ns entry point */
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/* x1 = ns entry point */
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@ -125,24 +86,12 @@ uint64_t tegra132_sip_handler(uint32_t smc_fid,
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INFO("CPU switched to AARCH%s mode\n",
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INFO("CPU switched to AARCH%s mode\n",
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(x2 == NS_SWITCH_AARCH32) ? "32" : "64");
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(x2 == NS_SWITCH_AARCH32) ? "32" : "64");
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SMC_RET1(handle, 0);
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return 0;
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break;
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default:
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default:
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ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
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ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
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break;
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break;
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}
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}
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SMC_RET1(handle, SMC_UNK);
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return -ENOTSUP;
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}
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}
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/* Define a runtime service descriptor for fast SMC calls */
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DECLARE_RT_SVC(
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tegra132_sip_fast,
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OEN_SIP_START,
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OEN_SIP_END,
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SMC_TYPE_FAST,
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NULL,
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tegra132_sip_handler
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);
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@ -51,7 +51,6 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
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${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
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${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
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${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \
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${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \
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${SOC_DIR}/plat_psci_handlers.c \
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${SOC_DIR}/plat_psci_handlers.c \
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${SOC_DIR}/plat_sip_calls.c \
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${SOC_DIR}/plat_setup.c \
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${SOC_DIR}/plat_setup.c \
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${SOC_DIR}/plat_secondary.c
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${SOC_DIR}/plat_secondary.c
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